Patents Examined by William Bunch
  • Patent number: 4795722
    Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: January 3, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr., Jeffrey E. Brighton
  • Patent number: 4793872
    Abstract: A component of semiconductor material deposited by epitaxial growth on a substrate having a predetermined and different lattice parameter consists of an alternate succession of layers of a first type and layers of a second type deposited on the substrate. The lattice parameter of the first type of layers is substantially matched with the lattice parameter of the substrate. In the case of the second type of layers, the lattice parameter is matched and even equal to that of the first type of layers. A component having a lattice parameter equal to that of the second type of layers is formed on the last layer of the second type. Moreover, the energy gaps of the two types of layers are different.
    Type: Grant
    Filed: March 4, 1987
    Date of Patent: December 27, 1988
    Assignee: Thomson-CSF
    Inventors: Paul L. Meunier, Manijeh Razeghi
  • Patent number: 4789645
    Abstract: During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps.
    Type: Grant
    Filed: April 20, 1987
    Date of Patent: December 6, 1988
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, Ronald J. Pomian
  • Patent number: 4786616
    Abstract: A method for epitaxially growing a layer of III-V material on a wafer of a material such as silicon comprises the steps of placing the wafer (16') in a first ultra-high vacuum chamber (11), and epitaxially growing a transition layer such as germanium on the wafer. An intermediate high vacuum chamber (13) is used to transport the wafer 16' to a second ultra-high vacuum chamber (12), and the second chamber (12) is used to epitaxially grow a layer of III-V material over the transition layer. Gate valves (33 and 15) are sequentially opened and closed to that the second vacuum chamber (12) cannot be contaminated by gases or particles from the first vacuum chamber (11). Wafer transport from chamber (11) to (13) is achieved without exposure to the atmosphere or to significant pressure changes thus avoiding the waste of transfer time or the formation of native oxide on the wafer surface.
    Type: Grant
    Filed: June 12, 1987
    Date of Patent: November 22, 1988
    Assignee: American Telephone and Telegraph Company
    Inventors: Muhammad A. Awal, El Hang Lee
  • Patent number: 4786612
    Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.
    Type: Grant
    Filed: December 29, 1987
    Date of Patent: November 22, 1988
    Assignee: Intel Corporation
    Inventors: Leopoldo D. Yau, Shih-Ou Chen, Yih S. Lin
  • Patent number: 4786615
    Abstract: A method for growing selective epitaxial silicon by chemical vapor deposition resulting in a substantially planar surface by growing superimposed silicon layers at temperatures above and below a transition point.
    Type: Grant
    Filed: August 31, 1987
    Date of Patent: November 22, 1988
    Assignee: Motorola Inc.
    Inventors: Hang M. Liaw, Ha T.-T. Nguyen
  • Patent number: 4782035
    Abstract: A method for producing a semiconductor laser comprising depositing a first semiconductor layer comprising n-type InP on an n-type InP substrate, depositing a diffraction grating of InGaAsP which includes or excludes doping impurities on the first semiconductor layer with irradiating interference fringes by a light excitation crystalline growth means, and burying a portion of the diffraction grating with InGaAsP including or excluding doping impurities with irradiating interference fringes reverse in light and darkness from said interference fringes used in depositing the diffraction grating.
    Type: Grant
    Filed: November 12, 1987
    Date of Patent: November 1, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masatoshi Fujiwara
  • Patent number: 4782034
    Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by an MOCVD process through the use of bis arene titanium sources, such as cyclopentadienyl cycloheptatrienyl titanium and bis (benzene) titanium.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: November 1, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Andrew G. Dentai, Charles H. Joyner, Jr., Timothy W. Weidman, John L. Zilko
  • Patent number: 4780425
    Abstract: The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved.
    Type: Grant
    Filed: November 12, 1987
    Date of Patent: October 25, 1988
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Teruo Tabata
  • Patent number: 4778775
    Abstract: Improved processing for forming an interconnect in a process where a recrystallized polysilicon layer is formed over an insulative layer and where recrystallization takes place through a plurality of seed windows formed in the insulative layer. A doped region is formed in the substrate prior to deposition of the polysilicon layer. The polysilicon layer is in contact with at least a portion of the doped region through an opening in the insulative layer. Recrystallization takes place through this opening, and, for instance, the doped region is electrically connected to a source or drain region of a semiconductor device formed in the recrystallized layer.
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: October 18, 1988
    Assignee: Intel Corporation
    Inventor: J. C. Tzeng
  • Patent number: 4777148
    Abstract: A distributed feedback (DFB) type laser and a method and apparatus for forming same wherein a quaternary semiconductor active lasing strip of material is buried between a substrate of binary compound of one type conductivity material and a mesa binary compound body of opposite type conductivity and a periodic grating structure is etched into the plateau of the mesa. In one embodiment, ohmic contacts are provided on either side of the grating structure and the mesa is undercut adjacent the active strip to partly isolate the ohmic contacts from the homojunction formed when the active strip is buried, preferably using a mass-transport process. In another embodiment, the ohmic contacts are formed on the top of a deeply etched grating structure. A buried layer double heterostructure (DH) laser is also described with DFB grating formed on the side walls of the layer. Additionally, a surface emitting diode laser with DFB is described.
    Type: Grant
    Filed: September 1, 1987
    Date of Patent: October 11, 1988
    Assignee: Massachusetts Institute of Technology
    Inventors: Zong-Long Liau, Dale C. Flanders, James N. Walpole
  • Patent number: 4774205
    Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication.
    Type: Grant
    Filed: June 13, 1986
    Date of Patent: September 27, 1988
    Assignee: Massachusetts Institute of Technology
    Inventors: Hong K. Choi, Bor-Yeu Tsaur, George W. Turner
  • Patent number: 4771013
    Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.
    Type: Grant
    Filed: August 1, 1986
    Date of Patent: September 13, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick A. Curran
  • Patent number: 4769341
    Abstract: A semiconductor device comprising an epitaxially grown tin and Group IV compound semiconductor region on which at least one other semiconductor is grown lattice matched to the adjacent portion of the tin containing region. A large number of semiconductors may thus be grown.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: September 6, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Sergey Luryi
  • Patent number: 4769342
    Abstract: A semiconductor laser device comprises a substrate (7) formed of p type GaAs, a laser diode portion (10) capable of laser oscillation and a monitor photodiode portion (11) capable of photoelectric conversion formed on substrate (7). The laser diode portion (10) and the monitor photodiode portion (11) are both formed of an epitaxial separating layer (6) of p type AlAs, an epitaxial layer group (23) mainly formed of a material of AlGaAs system and an epitaxial window layer (9) formed on a cleavage plane of this epitaxial layer group (23). The cleavage plane of the epitaxial window layer (9) on the side of the laser diode portion (10) constitutes a laser resonator plane (16) for laser light output of said laser diode portion (10) while the cleavage plane of the epitaxial window layer (9) on the monitor photodiode portion (11) constitutes a light receiving plane (17) for receiving the laser light outputted from the laser resonator plane (16).
    Type: Grant
    Filed: October 10, 1986
    Date of Patent: September 6, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Yagi, Hitoshi Kagawa
  • Patent number: 4766092
    Abstract: When a semiconductor device is produced by growing epitaxially a compound semiconductor layer on a Si or Ge substrate, lattice matching between the substrate crystal and the compound semiconductor layer to be formed on the substrate can be improved by ion-implanting an ion species element, which increases the lattice constant of Si or Ge as the substrate, into the Si or Ge substrate in order to increase its lattice constant. In comparison with conventional semiconductor devices using Si or Ge into which ion implantation is not made, the semiconductor device produced by the method described above can improve remarkably its characteristics. In the case of a semiconductor laser device, for example, its threshold value drops drastically and its service life can be prolonged remarkably.
    Type: Grant
    Filed: December 2, 1986
    Date of Patent: August 23, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Takao Kuroda, Kenji Hiruma, Hiroyoshi Matsumura
  • Patent number: 4762807
    Abstract: An insulated-gate field effect transistor (IGFET) having the structure of the source and drain disposed in the longitudinal direction, i.e., the laminating direction, so that the channel region extends in the lateral direction when a high voltage is applied. This structure prevents a high current density at the interface of the channel region and the gate insulation film, allowing the fabrication of a large-current power transistor or the integration of such transistors.
    Type: Grant
    Filed: August 13, 1986
    Date of Patent: August 9, 1988
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 4760036
    Abstract: A process for growing silicon on insulator in which complete isolation of the grown silicon of the substrate silicon by an intermediate oxide layer is obtained. A first epitaxial lateral overgrowth technique is used to grow a continuous layer of silicon through seed holes in a patterned oxide layer overlying the silicon substrate. Then the silicon layer is etched to expose the seed holes which are then oxidized to make the oxide layer aperture-free. This is followed by a second epitaxial lateral overgrowth step to replace the silicon etched in the silicon layer to make the layer substantially planar.
    Type: Grant
    Filed: June 15, 1987
    Date of Patent: July 26, 1988
    Assignee: Delco Electronics Corporation
    Inventor: Peter J. Schubert
  • Patent number: 4758532
    Abstract: A semiconductor laser device comprises a substrate (7) formed of p type GaAs, a laser diode portion (10) capable of laser oscillation and a monitor photodiode portion (11) capable of photoelectric conversion formed on substrate (7). The laser diode portion (10) and the monitor photodiode portion (11) are both formed of an epitaxial separating layer (6) of p type AlAs, an epitaxial layer group (23) mainly formed of a material of AlGaAs system and an epitaxial window layer (9) formed on a cleavage plane of this epitaxial layer group (23). The cleavage plane of the epitaxial window layer (9) on the side of the laser diode portion (10) constitutes a laser resonator plane (16) for laser light output of said laser diode portion (10) while the cleavage plane of the epitaxial window layer (9) on the monitor photodiode portion (11) constitutes a light receiving plane (17) for receiving the laser light outputted from the laser resonator plane (16).
    Type: Grant
    Filed: September 2, 1987
    Date of Patent: July 19, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Yagi, Hitoshi Kagawa
  • Patent number: 4757030
    Abstract: Solid phase epitaxial growth of single crystal layers on single crystal semiconductor substrates at temperatures low enough to preserve the integrity of other entities on the substrates. Contaminants are removed by low energy ion sputtering at a pressure low enough to delay their reformation before the layer can be deposited on the surface followed by annealing for one hour at 400.degree. C. A method of solid phase epitaxially growing a single crystal layer on a single crystal semiconductor substrate is also disclosed.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: July 12, 1988
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Gregory J. Galvin, Christopher J. Palmstrom