Abstract: A display panel and a method for manufacturing the same and a display device are disclosed. The display substrate includes: a base substrate having a plurality of pixel areas, at least one of the plurality of pixel areas including a first electrode layer, an organic functional layer and a second electrode layer stacked in sequence on the base substrate; and a third electrode layer on a side of the second electrode layer facing away from the base substrate; wherein the third electrode layer is electrically connected to the second electrode layer.

Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

Abstract: A semiconductor device is provided to reduce thermal fatigue in a junction portion of an external wiring to enhance long-term reliability, where the semiconductor device includes a semiconductor substrate, a transistor portion and a diode portion that are alternately arranged along a first direction parallel to a front surface of the semiconductor substrate inside the semiconductor substrate, a surface electrode that is provided above the transistor portion and the diode portion and that is electrically connected to the transistor portion and the diode portion, an external wiring that is joined to the surface electrode and that has a contact width with the surface electrode in the first direction, the contact width being larger than at least one of a width of the transistor portion in the first direction and a width of the diode portion in the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Abstract: Provided are a light emitting diode (LED) in which a conductive barrier layer surrounding a reflective metal layer is defined by a protective insulating layer, and a method of manufacturing the same. A reflection pattern including a reflective metal layer and a conductive barrier layer is formed on an emission structure in which a first semiconductor layer, an active layer, and a second semiconductor layer are formed. The conductive barrier layer prevents diffusion of a reflective metal layer and extends to a protective insulating layer recessed under a photoresist pattern having an overhang structure during a forming process. Accordingly, a phenomenon where the conductive barrier layer is in contact with sidewalls of the photoresist pattern having an over-hang structure and the reflective metal layer forms points is prevented. Thus, LED modules having various shapes may be manufactured.

Abstract: Some embodiments include an assembly having a channel to conduct current. The channel includes a first channel portion and a second channel portion. A first memory cell structure is between a first gate and the first channel portion. The first memory cell structure includes a first charge-storage region and a first charge-blocking region. A second memory cell structure is between a second gate and the second channel portion. The second memory cell structure includes a second charge-storage region and a second charge-blocking region. The first and second charge-blocking regions include silicon oxynitride. A void is located between the first and second gates, and between the first and second memory cell structures. Some embodiments include memory arrays (e.g., NAND memory arrays), and some embodiments include methods of forming memory arrays.

Abstract: A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip.

Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.

Abstract: A front surface of a semiconductor wafer is momentarily heated by irradiation with a flash of light from flash lamps. An upper radiation thermometer and a high-speed radiation thermometer unit measure a temperature of the front surface of the semiconductor wafer after the irradiation with the flash of light. The temperature data are sequentially accumulated, so that a temperature profile is acquired. An analyzer determines the highest measurement temperature of the semiconductor wafer subjected to the flash irradiation from the temperature profile to calculate a jump distance of the semiconductor wafer from a susceptor, based on the highest measurement temperature. If the calculated jump distance is greater than a predetermined threshold value, there is a high probability that the semiconductor wafer is significantly out of position, so that the transport of the semiconductor wafer to the outside is stopped.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.

Abstract: A display device includes a base substrate including a front surface having an active area and a peripheral area; a plurality of pixels; a plurality of first signal lines on the active area, each extending in a first direction, spaced apart from each other in a second direction crossing the first direction; a plurality of second signal lines, crossing the first signal line in an insulation manner; a plurality of first conductive patterns, spaced apart from each other in the first direction; a second conductive pattern overlapping the first conductive patterns and having a top surface waved in the first direction; and an optical member on the second conductive pattern, wherein the top surface of the second conductive pattern includes flat portions and protruding portions, that are alternately arranged in the first direction, and the protruding portions protrude from the flat portions toward the optical member.

Abstract: A film package includes a film substrate, a first semiconductor chip on a first surface of the film substrate, a second semiconductor chip on the first surface of the film substrate, and a first conductive film on the first surface of the film substrate. The first conductive film covers the first semiconductor chip and the second semiconductor chip and includes a slit(s) or a notch(es). The slit(s) or notch(es) is/are disposed in a bridge region between the first semiconductor chip and the second semiconductor chip, in a plan view of the package.

Abstract: A semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, a source electrode, a drain electrode and a gate structure. The channel layer, the first barrier layer, and the second barrier layer are sequentially stacked over a substrate. The source electrode, a drain electrode and the gate structure extend through at least portions of the second barrier layer. The source electrode, the drain electrode and the gate structure have respective bottom surfaces located at substantially the same level as and adjacent to the first barrier layer.

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

Abstract: A light-emitting module for an automotive vehicle includes a light source including a plurality of electroluminescent rods, and a layer adapted for encapsulating the electroluminescent rods and for converting at least a portion of the light emitted by the rods into a converted light, the layer including a conversion sublayer extending beyond a free end of the electroluminescent rods, the conversion sublayer including a phosphor compound adapted for generating the converted light from the light emitted by the electroluminescent rods, the phosphor compound being in the form of grains, the dimensions of which are provided to prevent the presence of the grains between spaces delimited laterally between the rods, and an encapsulation sublayer in which at least a portion of the electroluminescent rods is embedded.

Abstract: Aspects of the disclosure include methods of processing a substrate. The method includes depositing a conformal layer on a substrate which contains seams. The substrate is treated using a high pressure anneal in the presence of an oxidizer.

Abstract: The semiconductor device include a lower insulating layer; a gate stack disposed over the lower insulating layer; a plurality of supports extending from the lower insulating layer toward the gate stack; a source layer disposed between the lower insulating layer and the gate stack; and a channel pattern including a connection part disposed between the source layer and the gate stack.

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

Abstract: A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a conductive foil bonded to the semiconductor region.

Abstract: An embodiment provides a method of predicting a thickness of an oxide layer of a silicon wafer including: aging a heat treatment furnace (furnace); measuring a thickness of each of the oxide layers after disposing a plurality of reference wafers in slots of a heat treatment boat in the furnace and forming oxide layers; and measuring a thickness of each of the oxide layers after disposing the plurality of reference wafers and test wafers in the slots of the heat treatment boat in the furnace and forming oxide layers.