Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.

Abstract: A method for texturing a photovoltaic module ribbon on a photovoltaic cell including a plurality of first electrodes on a first side and a plurality of second electrodes on a second side, and coupling a first photovoltaic module ribbon to the plurality of first electrodes. The method also includes positioning the photovoltaic cell on a textured base having a texture embodied thereon, where the first photovoltaic module ribbon is substantially contacting the texture. The method further includes coupling a second photovoltaic module ribbon to the plurality of second electrodes, and transferring the texture of the textured base to the first ribbon using heat energy released when the second photovoltaic module ribbon is coupled to the plurality of second electrodes.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

Abstract: A high-pressure processing system for processing a substrate includes a first chamber, a pedestal positioned within the first chamber to support the substrate, a second chamber adjacent the first chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, and a gas delivery system configured to introduce a processing gas into the first chamber and to increase the pressure within the first chamber to at least 10 atmospheres while the processing gas is in the first chamber and while the first chamber is isolated from the second chamber.

Abstract: Methods and apparatuses for substrate fabrication are provided herein.

Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

Abstract: A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.

Abstract: A purging method for purging an interior of a processing container of a substrate processing apparatus after a film forming process is executed on a wafer in the processing container, includes a first process of pressurizing a first gas in a first line of the substrate processing apparatus and then discharging the first gas into the processing container, and a second process of supplying a second gas into the processing container. The second process is executed after execution of the first process, the first gas includes an inert gas, and the second gas includes a hydrogen gas, a nitrogen-containing gas, a rare gas or a combination of these gases.

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.

Abstract: An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Abstract: A semiconductor device includes a semiconductor substrate, a filling conductor, an N-work function conductor layer and a gate dielectric layer. The filling conductor is over the semiconductor substrate. The N-work function conductor layer wraps around the filling conductor. The N-work function conductor layer comprises chlorine. The gate dielectric layer is between the N-work function conductor layer and the semiconductor.

Abstract: A monolithically integrated multi-sensor (MIMS) is disclosed. A MIMs integrated circuit comprises a plurality of sensors. For example, the integrated circuit can comprise three or more sensors where each sensor measures a different parameter. The three or more sensors can share one or more layers to form each sensor structure. In one embodiment, the three or more sensors can comprise MEMs sensor structures. Examples of the sensors that can be formed on a MIMs integrated circuit are an inertial sensor, a pressure sensor, a tactile sensor, a humidity sensor, a temperature sensor, a microphone, a force sensor, a load sensor, a magnetic sensor, a flow sensor, a light sensor, an electric field sensor, an electrical impedance sensor, a galvanic skin response sensor, a chemical sensor, a gas sensor, a liquid sensor, a solids sensor, and a biological sensor.

Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

Abstract: Disclosed herein is an organic light-emitting display device having a first flexible substrate; a second flexible substrate; a plurality of organic light-emitting pixels on the first flexible substrate and between the first flexible substrate and the second flexible substrate; an encapsulation unit covering the pixels; and an adhesive layer on the encapsulation unit. The Young's modulus of the adhesive layer is equal to or larger than a value so that the first flexible substrate is not deformed by bending stress when it is rolled up.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device which ensure improved reliability, permit further miniaturization, and suppress the increase in manufacturing cost. The semiconductor device includes: a pad electrode formed in the uppermost wiring layer of a multilayer wiring layer formed over a semiconductor substrate; a surface protective film formed in a manner to cover the pad electrode; an opening made in the surface protective film in a manner to expose the pad electrode partially; and a conductive layer formed over the pad electrode exposed at the bottom of the opening. The thickness of the conductive layer formed over the pad electrode is smaller than the thickness of the surface protective film formed over the pad electrode.

Abstract: A light emitting element according to an embodiment of the present invention comprises a first conductive-type semiconductor layer including a contact region on the lower surface thereof, a light emitting structure which includes a mesa including a second conductive-type semiconductor layer and an active layer, a second electrode, a first insulation layer, an electrode cover layer, a first electrode, a second insulation layer, and a support structure. In addition, the mesa may include a body part and a plurality of protrusion parts protruding from the body part, the contact region may be disposed between the protrusion parts, and a part of the contact region may overlap with a second metal bulk in the vertical direction. Accordingly, current spreading efficiency can be improved, and thus luminance efficiency can be more improved.