Patents Examined by William D. Larkins
  • Patent number: 5736773
    Abstract: A photodiode having an antireflection coating for use in optical measuring devices has its antireflection coating so selected that it provides in a predetermined wavelength range an approximately constant conversion factor. The conversion of the fight power to an electrical signal is thus substantially independent of wavelength over this wavelength range.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: April 7, 1998
    Assignee: Wandel & Goltermann GmbH & Co. Elektronische Messtechnik
    Inventor: Wolfgang Schmid
  • Patent number: 5610366
    Abstract: Transition metals (T) of Group VIII (Co, Rh and Ir) have been prepared as semiconductor alloys with Sb having the general formula TSb.sub.3. The skutterudite-type crystal lattice structure of these semiconductor alloys and their enhanced thermoelectric properties results in semiconductor materials which may be used in the fabrication of thermoelectric elements to substantially improve the efficiency of the resulting thermoelectric device. Semiconductor alloys having the desired skutterudite-type crystal lattice structure may be prepared in accordance with the present invention by using vertical gradient freeze techniques, liquid-solid phase sintering techniques, low temperature powder sintering and/or hot-pressing. Measurements of electrical and thermal transport properties of selected semiconductor materials prepared in accordance with the present invention, demonstrated high Hall mobilities (up to 8000 cm.sup.2.V.sup.-1.s.sup.-1), good Seebeck coefficients (up to 400 .mu.VK.sup.-1 between 300.degree. C.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: March 11, 1997
    Assignee: California Institute of Technology
    Inventors: Jean-Pierre Fleurial, Thierry F. Caillat, Alexander Borshchevsky
  • Patent number: 5610433
    Abstract: A high value inductor with a high Q factor is formed using integrated circuit techniques to have a plurality of layers, where each layer has formed on it two or more coils. The coils in the various layers are interconnected in series. Although the resulting inductor exhibits a relatively high resistance, the number of coil turns is large. Since inductance increases in proportion to the square of the number of coil turns, the resulting inductor has a very high Q factor. A cross-over arrangement located in one level provides compact connections between turns in a different level.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: March 11, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Richard B. Merrill, Enayet U. Issaq
  • Patent number: 5602413
    Abstract: A bipolar avalanche phototransistor has a thin, heavily doped base portion adjacent the collector to improve avalanche characteristics. The structure may have a lateral, as well as vertical, collector, with the thin heavily doped base portion adjoining the surface lateral collector.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: February 11, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Morishita
  • Patent number: 5600152
    Abstract: In order to reduce the dark current due to an interfacial defect and effect higher sensitivity, there is disclosed a manufacturing method for a photoelectric conversion device having a light absorbing layer and a carrier multiplying layer at least having a non-single crystalline semiconductor, the carrier multiplying layer being composed of a plurality of graded layers of which the forbidden band width continuously changes from the minimum forbidden band width Eg1 to the maximum forbidden band width Eg2, wherein there is an energy step sufficient to avalanche multiply the carriers between a region of the maximum forbidden band width Eg2 and a region of the minimum forbidden band width Eg1 adjacent thereto, when an electric field is applied, characterized in that after the deposition of any one of the region of the minimum forbidden band width Eg1 and the region of the maximum forbidden band width Eg2, the plasma treatment is performed with a gas at least containing oxygen or nitrogen, and further the other re
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: February 4, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiraku Kozuka, Shigetoshi Sugawa
  • Patent number: 5596217
    Abstract: A semiconductor device includes a diode element for protecting a transistor against an overvoltage. A first region of p-type conductivity is formed on an upper surface of an n-type semiconductor substrate in which base and emitter regions of the transistor are formed. A second region of n.sup.+ -type conductivity whose impurity concentration is higher than that of the n-type semiconductor substrate is formed on its upper surface to be spaced apart from the first region. An insulating film is formed to cover the upper surface of the semiconductor substrate. Furthermore, a conductive film is formed to partially overlap the first and second regions through the insulating film. The first region serves as an anode, the second region serves as a cathode, and the conductive film serves as a gate electrode; thus an overvoltage protection diode is obtained.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: January 21, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Masami Yamaoka, Shoji Toyoshima
  • Patent number: 5596522
    Abstract: A unique class of microcrystalline semiconductor materials which can be modulated, within a crystalline phase, to assume any one of a large dynamic range of different Fermi level positions while maintaining a substantially constant band gap over the entire range, even after a modulating field has been removed. A solid state, directly overwritable, electronic and optical, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory based upon the novel switching characteristics provided by said unique class of semiconductor materials, which memory exhibits orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory of the instant invention is in turn characterized, inter alia, by numerous stable and non-volatile detectable configurations of local atomic order, which configurations can be selectively and repeatably accessed by input signals of varying levels.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: January 21, 1997
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, Stephen J. Hudgens, David Strand, Wolodymyr Czubatyj, Jesus Gonzalez-Hernandez, Hellmut Fritzsche, Quiyi Ye, Sergey A. Kostylev, Benjamin S. Chao
  • Patent number: 5587600
    Abstract: A read-only-memory having a plurality of very narrow, closely spaced gate electrodes spanning the distance between source and drain regions. The gate electrodes consist of first and second alternating polycrystalline silicon lines having vertical sidewalls. The first lines have tapered sidewall spacers. The second lines are entirely contained between the first lines without overlap of the first lines.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: December 24, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Ming T. Yang
  • Patent number: 5585654
    Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.
    Type: Grant
    Filed: October 24, 1991
    Date of Patent: December 17, 1996
    Assignee: Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5573601
    Abstract: A pin type photovoltaic element having an electroconductive substrate and a cell stacked with an n-type semiconductor layer, an i-type semiconductor layer and a p-type semiconductor, all composed of a non-single crystal material containing silicon, and featuring an intermediate layer. The intermediate layer composed of non-single material containing silicon atoms as the matrix and atoms of elements belonging to Group IIIA and VA of the periodic table is between the i-type conductor layer and the p-type conductor layer or the n-type semiconductor layer. The intermediate layer may contain carbon atoms and/or germanium atoms.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: November 12, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saitoh, Tatsuyuki Aoike, Yasushi Fujioka, Masafumi Sano, Mitsuyuki Niwa
  • Patent number: 5557119
    Abstract: A field effect transistor has the property that the product of its active total series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of this transistor, the active total series resistance being the sum of the active resistance from source to channel, the active resistance of this channel and the active resistance from channel to drain. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in such fashion in response to a small increase in the reverse gate voltage applied, that no narrow lengthy path is formed between the depletion layers. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: September 17, 1996
    Assignee: Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 5552623
    Abstract: A semiconductor device having a source region, a drain region and a channel region which are formed in a surface portion of a semiconductor substrate, and a gate formed with a material having a relatively high built-in voltage relative to the source region. This semiconductor device may further include, in the semiconductor substrate to extend along the channel region, a highly-doped region having a conductivity type opposite to that of the source region. This highly-closed region may have an impurity concentration gradient which is greater toward its portion facing the abovesaid surface of the substrate. These arrangements serve to prevent extinction of memory due to current leakage during absence of bias voltage which otherwise would develop in semiconductor devices having short-channel and thin gate oxide layer, and due to irradiation of alpha-particle onto the device.
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: September 3, 1996
    Assignee: Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 5543749
    Abstract: A heterojunction semiconductor device includes an unipolar transistor having, a collector layer, a base layer, a collector side barrier layer provided between the collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between the base layer and the emitter layer. The emitter side barrier layer has a thickness for tunneling a carrier from the emitter and base layer and injecting the carrier into the base layer according to a predetermined voltage applied between the emitter and base layers, the base layer includes a superlattice structure. The superlattice structure includes a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: August 6, 1996
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 5536947
    Abstract: An electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within the dynamic range in response to selected electrical input signals so as to provide the single cell with multibit storage capabilities, and (3) the ability of at least a filamentary portion to be set, by the selected electrical singal to any resistance value in the dynamic range, regardless of the previous resistance value of the material. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: July 16, 1996
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Patrick K. Klersy, David A. Strand, Stanford R. Ovshinsky
  • Patent number: 5534732
    Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: July 9, 1996
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, Jenifer E. Lary, Edmund J. Sprogis
  • Patent number: 5534711
    Abstract: The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the singIe cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: July 9, 1996
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, David A. Strand, Wolodymyr Czubatyj, Patrick Klersy
  • Patent number: 5534712
    Abstract: Disclosed herein is a solid state, directly overwritable, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, single cell memory element having reduced switching current requirements and an increased thermal stability of data retention. The memory element includes a volume of memory material which is a transition metal modified chalcogen. The transition metal may be selected from the group consisting of Nb, Pd, Pt and mixtures or alloys thereof. The memory material may further include at least one transition metal selected from the group consisting of Fe, Cr, Ni and mixtures or alloys thereof. The memory element exhibits orders of magnitude higher switching speeds at remarkably reduced switching energy levels.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: July 9, 1996
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Stanford R. Ovshinsky, David A. Strand, Patrick Klersy
  • Patent number: 5530267
    Abstract: We have discovered advantageous substrates for III-V nitride semiconductors such as GaN. The substrate material is of the YbFe.sub.2 O.sub.4 or InFeO.sub.3 (ZnO).sub.n structure type and has general composition RAO.sub.3 (MO).sub.n, where R is one or more of Sc, In, Y and the lanthanides (atomic number 67-71); A is one or more of Fe(III), Ga, and Al; M is one or more of Mg, Mn, Fe(II), Co, Cu, Zn and Cd; and n is an integer.gtoreq.1, typically<9. Furthermore, the substrate material is selected to have a lattice constant that provides less than .+-.5% lattice mismatch with the III-V nitride semiconductor material that is to be deposited thereon. At least some of the substrate materials (e.g., ScMgAlO.sub.4) typically can be readily and relatively cheaply produced in single crystal form, are readily clearable on the basal plane, and do essentially not interact chemically with the III-V nitride under typical deposition conditions.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: June 25, 1996
    Assignee: AT&T Corp.
    Inventors: Charles D. Brandle, Jr., Denis N. Buchanan, Elliot H. Hartford, Jr., Eric S. Hellman, Lynn F. Schneemeyer
  • Patent number: 5521735
    Abstract: Novel electron wave combining and/or branching devices and Aharonov-Bohm type quantum interference devices are proposed, which have no curved electron waveguide structures to form an electron branching or decoupling part or ring geometry. But instead the electron branching part or ring geometry is effectively constructed in a straight double quantum well structures, by the control of the shapes of the wave functions or of the subband energy levels relative to the Fermi level by electric fields.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: May 28, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Shimizu, Masahiro Okuda, Kazuhito Fujii
  • Patent number: 5517040
    Abstract: A computer converts a description of an analog circuit to a physical representation in terms of devices on a personalizable chip. The devices are placed and wired automatically for fabrication of the chip. Descriptions of resistors in the circuit are expanded by wiring multiple contacts of one or more actual resistor devices on the chip. The chip uses multiple rows of devices arranged in columns; each row contains multiple transistor and resistor devices.
    Type: Grant
    Filed: October 21, 1991
    Date of Patent: May 14, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Hedman, Gordon G. Koehler, Karl L. Ladin, John T. Trnka