Abstract: A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

Abstract: A semiconductor device having a high voltage MOS transistor comprise a first conductivity type semiconductor substrate; a second conductivity type tub formed in the first conductivity type semiconductor substrate; first conductivity type source/drain regions formed in the second conductivity type tub; and first conductivity type drift layers connected with either of the first conductivity type source/drain regions; wherein the second conductivity type tub has slit portions having a low impurity concentration in the neighborhood of the first conductivity type drift layer, whose impurity concentration is at the same level to that of the inside of the second conductivity type tub.

Abstract: A thick-oxide ESD transistor for a BiCMOS integrated circuit has its source/drain contacts formed of the BiCMOS base or emitter polysilicon and its source/drain formed by an outdiffusion of the respective polysilicon contact. In one embodiment the BiCMOS resistor doping deepens the ESD source/drains, and in another embodiment the BiCMOS collector reach through doping deepens the ESD source/drains. The entire ESD transistor is fabricated from a standard BiCMOS process without any additional steps, has an area of about 100 square microns, can shunt up to 6000 volts, and has a turn-on time of about 10 picoseconds.

Abstract: Disclosed are a noise eliminating element having a junction of components of two kinds of electroconductive materials, characterized in that the absolute values of the thermoelectric power of the two kinds of materials is 50 .mu.VK.sup.-1 or higher and there is substantially no rectifying action at the junction. Both the Seebeck effect and the Paltier effect occur simultaneous and create a transient phenomena in one element. Because of the transient phenomena in one element and because of the transient phenomenon based on both effects, noises, particularly the standing wave noises generated at around output current near to zero are eliminated. The noise eliminating elements can be inserted in a magnetic circuit of a speaker circuit for acoustic equipment or in a deflecting coil circuit of an electron image display device.

Abstract: A floating gate EPROM has surface source and drain regions, with a trench between the source and drain regions containing the floating and control gates. A thin tunneling oxide layer is located at the bottom of the trench and on the sidewalls of the trench adjacent the source and drain regions, with thicker gate oxide elsewhere in the trench.

Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.

Abstract: A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.

Abstract: An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode of one or more Zener diodes. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting Zener diodes are coupled together in an ESD structure using the second level busses and the thick copper third level busses.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: A manufacturing method for a semiconductor optical component in which ridge-shaped semiconductor light amplifier sections and ridge-shaped semiconductor waveguides connected thereto are integrated on the same substrate includes the steps of forming the ridge-shaped semiconductor light amplifier sections having a path width narrower than that of the ridge-shaped semiconductor waveguide at the appropriate positions on the substrate on which the ridge-shaped semiconductor light amplifier sections are to be formed; and forming the ridge-shaped semiconductor waveguide at the remaining positions other than the appropriate positions so as to connect to the ridge-shaped semiconductor light amplifier sections. The semiconductor optical component manufactured by this method provides high current density because the confining of the current injected to the light amplifier is strengthened.

Abstract: This invention is related to a III-V type of compound semiconductor device, having improved heat dissipation and high power operating characteristics, which is comprised of a semi-insulating III-V compound semiconductor wafer substrate having a frontside and a backside, a compound semiconductor etch stop layer, having an etch rate much slower than that of the wafer substrate, epitaxially grown on the frontside of said wafer substrate, an active compound semiconductor device consisted of at least two layers of compound semiconductor material epitaxially grown on the said etch stop layer, wells on the backside of said wafer substrate located underneath heat generating regions of said active device, wherein the wells are formed by etching action until the depth of wells reach said etch stop layer, and a heat conducting material disposed said wells.

Abstract: A resin-sealed semiconductor device, including a chip mounting die pad, porous fluorocarbon material located just beneath the die pad, beneath a die-pad supporting layer, gold lead wires, or in a sealing resin surrounding the other components, wherein any water vapor generated by the heat of soldering will be held within the porous fluorocarbon rather than crack the sealant under internal pressure.

Abstract: Gate width directions of transistors are taken in circumferential directions surrounding a certain point as a center. Or transistors are constructed by a plurality of straight lines extending in radial directions of the certain point and intersecting each other at the same angle. Hereby, basic cells can be assembled on a master slice symmetrically in plural directions. There are arranged in a mutual adjacent relation in which channel layers located under one opposing gate electrodes are formed into P channels and channel layers located under the other opposing gate electrodes are formed into N channels. Otherwise, there are arranged alternately with respect to P channels and N channels in an adjacent relation basic cells in which all channel layers located under all gate electrodes in the same basic cell are formed by any type of the P channel and the N channel.

Abstract: A lightly doped drain MOSFET has lightly doped portions on both the source and drain sides, with the drain side lightly doped portion being wider. The assymetrical structure may be provided by using different width sidewall spacers.

Abstract: A method of fabricating a high-density multilayer copper/polyimide interconnect structure utilizing a blanket tantalum/tantalum oxide layer that electrically connects all of the electroplating seed layers to the edge of the substrate; upon completion of the electroplating process, the excess tantalum/tantalum oxide layer is etched off to produce isolated conductor lines. A multilayer copper/polyimide interconnect structure may be fabricated by repeating this fabrication sequence for each layer.

Abstract: A field plate avalanche diode has a field plate extending over the breakdown PN junction.

Abstract: A DRAM is formed on a silicon substrate having a retrograde well and a diffusion-type well. The retrograde well has an impurity concentration profile which is set in steps by a plurality of ion-implantations. The diffusion-type well has an impurity concentration profile which changes monotonously by a thermal diffusion. A memory cell array is formed in the retrograde well region. A peripheral circuit is formed in the diffusion-type well region. The retrograde well enhances integration of devices included in the memory cell array. The diffusion-type well enhances the characteristic of insulating isolation between devices.

Abstract: Disclosed is a memory having a p-type semiconductor substrate having a high impurity concentration a p-type semiconductor layer is formed on thereof; a groove which is formed so as to extend from a surface of the semiconductor layer to a position inside the semiconductor substrate; an impurity diffused region which is formed on portions of the semiconductor layer and the semiconductor substrate which define the groove; and an electrode which is formed from the groove to level at least above an opening of the groove through capacitor insulation film, the impurity diffused region, capacitor insulation film and electrode constituting trenched capacitor in which the electrode serves first capacitor electrode and the impurity diffused region serves as a second capacitor electrode.

Abstract: Disclosed is a semiconductor device wherein the down bonding and the mounting of multi-pin is made possible. A conductive member adhered to the bottom surface of the semiconductor element. The conductive member and the specific pad of the semiconductor element are connected by the connecting member, which enables the entire bottom surface of the semiconductor element to be used for down bonding. Further, the more effective latch-up suppression, noise dispersion and speed improvement compared with the conventional LOC-type package structure is possible.

Abstract: A semiconductor device provides for shielding of resistance elements as well as other elongated passive or active components formed in the structure by diffusion of impurities into a polycrystalline silicon layer or a semiconductor substrate and a conductor is formed on an upper surface of the resistance element having a resistance value lower than that of the formed resistance element. Also, the conductor is formed so as to hold a fixed potential value. This structure prevents an invasion or infiltration of impurities which causes a variation in the resistance value of the resistance element. Further, the conductor functions as shielding from noise from a signal line in close proximity to the resistance element or from external noise by means of fixing the conductor at a fixed potential value thereby maintaining the stability of the resistance value of the resistance element.