Abstract: An advanced MESFET switching structure which includes an interdigitated source region and an interdigitated drain region, also includes a gate electrode region disposed between adjacent portions of the interdigitated source and drain regions having a series gate electrode in Schottky barrier contact therewith. The use of the series connect gate electrode rather than conventional parallel coupled gate fingers eliminates the need for an airbridge overlays to interconnect the source regions as in a conventional MESFET transducer. Moreover, the topography permits smaller MESFET structures and thus higher integration of circuits employing the advanced MESFET switch structure. The smaller transistors will also have lower parasitic reactances. In a preferred embodiment, all interconnections for drain, gate, and source electrodes are disposed on the active layer portion of the transistor providing an even smaller transistor structure.

Abstract: An alignment key (10) in a semiconductor substrate (40) is fabricated to display high optical contrast, and to prevent the diffusion of ionic contaminants through the alignment key (10) and into underlying portions of the semiconductor substrate (40). The alignment key (10) defines an enclosed structure formed by first and second metal layers (14, 20) which are electrically coupled by a filled via (22). A dielectric layer (42) is disposed between the metal layers (14, 20). A passivation layer (16) overlies an edge portion of the upper metal layer (14), however, the central portion of the upper metal layer (14) is bare. Slots (11, 12) in the upper metal layer (14) expose a portion of the lower layer (20) through the dielectric material (42). A high contrast scan signal (24) is generated as a continuous-wave laser beam traverses across the upper metal layer (14) and the slots (11,12).

Abstract: A Gunn diode in which the conversion efficiency can be improved without lowering the reliability, by reducing the dead zone while maintaining n.sup.+ nn.sup.+ structure. In this Gunn diode, the donor impurity concentration in the n-type active layer is graded along a direction perpendicular to a contact plane between the n-type active layer and the n.sup.+ -type layers, and an average concentration gradient of the donor impurity concentration in the n-type active layer simultaneously satisfies the following two inequalities: G>(A.sub.1 N/L)exp(-NL/S.sub.1) and G<(A.sub.2 N/L)exp(-NL/S.sub.2), where L is a thickness of the n-type active layer, N is an average concentration of the donor impurity, S.sub.1 =0.87.times.10.sup.12 cm.sup.-2 is a constant, S.sub.2 =1.32.times.10.sup.12 cm.sup.-2 is a constant, A.sub.1 =2.0 is a constant, and A.sub.2 =9.0 is a constant.

Abstract: In order to obtain a logic circuit capable of performing a high-speed operation, respective gates of a P-channel MOSFET (1) and an N-channel MOSFET (2) are connected to an input node (6) in common, and ends of resistors (12, 13) are connected to respective drains thereof. Respective emitters of an NPN transistor (3) and a PNP transistor (4) are connected to an output node (9) with an end of a resistor (5) in common, and ends of the resistors (12, 13) are connected to respective bases thereof. A source of the P-channel MOSFET (1) and a collector of the NPN transistor (3) are connected to a high potential point (8) in common while a source of the N-channel MOSFET (2) and a collector of the PNP transistor (4) are connected to a low potential point (40) in common respectively. Respective other ends of the resistors (5, 12, 13) are connected at a node (7) in common. Thus, the potential of an output terminal quickly fluctuates when a bipolar transistor is in an ON state.

Abstract: A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Abstract: A first insulating layer (32), a first shield pattern (iii) and a second insulating layer (112) are layered on an aluminum substrate (31) in that order. A first and a second power switching element (1, 2), which are in totem pole like connection, are provided On the second insulating layer (112). Also provided on the second insulating layer (112) are a first and a second control circuit (13, 14), through a second and a third shield pattern (101, 104) as well as a third and a fourth insulating layer (105, 106). The first shield pattern (111) is kept at a certain reference potential, because .+-.he first shield pattern (11) connected to a power source terminal N. The second and the third shield pattern (101, 104) are kept at potentials corresponding to the potentials of the output terminals of the first and the second power switching element (1, 2), respectively.

Abstract: A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.

Abstract: A solid state, directly overwritable, electronic, non-volatile, high density, low cost, low energy, high speed, readily manufacturable, multibit single cell memory based upon phenomenologically novel electrical switching characteristics provided by a unique class of semiconductor materials in unique configurations, which memory exhibits orders of magnitude higher switching speeds at remarkably reduced energy levels. The novel memory of the instant invention is characterized, inter alia, by numerous stable and truly non-volatile detectable configurations of local atomic and/or electronic order, which can be selectively and repeatably accessed by electrical input signals of varying pulse voltage and duration.

Abstract: In an organic electroluminescent device including first and second electrodes opposite to each other and a multi-layered body which is sandwiched between these electrodes and consists of a plurality of organic films including a light-emitting layer, a material for each organic film and electrode is selected so that electrons and holes are simultaneously and respectively injected from the first and second electrodes in the multi-layered body when a forward biasing voltage is applied, a large amount of injected electrons and holes are accumulated at the multi-layered body, and these electrons and holes are subjected to radiative recombination at a predetermined threshold voltage.

Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.

Abstract: FETs and quantum well diodes are combined on the same semi-insulating substrate, while providing the FETs with protection from spurious voltages. A deeply buried P region in the semi-insulating substrate is partitioned by a high resistivity proton implanted region, to provide both the P region of the quantum well diode and an isolating buried P layer for the FETs.

Abstract: Electrical ohmic contacts are made to a matrix of silicon having conductive rods embedded therein without making contact to any of the rods. Those rods which extend to the surface in the selected area of the matrix to be contacted are etched to form holes. The holes are filled with insulating polycrystalline silicon. The region of the selected area is heavily doped, and an ohmic contact member is made thereto. The underlying rods are spaced from the ohmic contact member and the heavily-doped region by intervening polycrystalline silicon.

Abstract: A GaAs MESFET employs an etch stop layer of Ga.sub.0.99 In.sub.0.01 As over the channel region.

Abstract: A semiconductor device with a monocrystalline silicon body (1) is provided with a dielectric layer (2) with contact holes (3) through which the silicon body (1) is contacted with an aluminum metallization. To avoid undesirable separation of silicon, a discontinuous nucleus layer (5) of a metal nobler than silicon is formed on the silicon body (1) in the contact holes (3) preceding the provision of the metallization (4). Metals such as palladium and copper may be used to form the discontinuous layer.

Abstract: In a semiconductor light-emitting element having a double hetero junction structure of an InGaAP system an n-type dopant, which does not change a crystal structure, is doped in an In.sub.1-y (Ga.sub.1-x Al.sub.x).sub.y P(0.ltoreq.x<1, y.perspectiveto.0.5) active layer, so that an n-type active layer (4), is formed between a p-type InGaAlP cladding layer (5), which has band-gap energy that is larger than that of the active layer (4), and an n-type InGaAlP cladding layer (3), thereby preventing the dopant of the P-type InGaAlP cladding layer (3) from being dispersed into the active layer (4). Thus, the oscillation wavelength of the light-emitting element is not shifted to a short wavelength, and the threshold current of the oscillation is not increased thereby providing an element which can improve yield and reliance.

Abstract: A MOS device comprising a parallel array of a plurality of unit structures on a substrate, each unit structure including a first semiconductor layer of a first conductivity type, an oxide layer disposed on a major surface of the first semiconductor layer, a control electrode formed on the oxide layer, and second and third semiconductor layers separated from each other by the first semiconductor layer. The electric current flowing through a surface layer in contact with the oxide layer is controlled by the voltage applied to the control electrode, and the oxide layer is relatively thick between the first semiconductor layer and the control electrode on the periphery of the unit structures located on the periphery of the substrate and relatively thin between the first semiconductor layer and control electrode in other regions of the MOS device.

Abstract: A semiconductor device comprises a semiconductor substrate (11) having first and second field effect transistors. Each transistor includes a gate electrode (17, 18) formed on the semiconductor substrate with a gate insulating film (15, 16) interposed therebetween. A first side wall spacer (21, 22) formed of one layer of an insulating film on opposite side wall surface of the gate electrode, and source/drain regions (19, 24, 26, 30), each comprising high and/or low impurity concentration regions of the gate electrode (17, 18) on the surface of the semiconductor substrate (11). A second side wall spacer (27, 28) formed of another layer of an insulating film formed at least one side wall surface of the gate electrode (17, 18) of at least said second transistor. The first and/or the second side wall spacers (21, 22, 27, 28) form diffusion masks for adjusting distribution of impurity concentration of the transistors.

Abstract: A transferred electron effect device (1) has adjacent its cathode contact region (3) an injection zone (60) defining a potential barrier (P) for causing electrons to be emitted, under the influence of an electric field applied between the cathode and anode contact regions (3 and 4), into the active region (5) of the device with an energy comparable to that of a relatively high mass, low mobility satellite minimum (L) of the active region (5). The anode contact region (4), active region (5), injection zone (60) and cathode contact region (3) are grown sequentially, for example using molecular beam epitaxy, on a substrate which is then selectively removed to expose the anode contact region. A heat sink (70) is provided in thermal contact with the anode contact region (4). Providing the heat sink (70) in thermal contact with the anode contact region (4) rather than the cathode contact region (3) enables a significant increase in rf output power.

Abstract: A channel stop is self-aligned with a trench sidewall of a trench-isolated semiconductor architecture, so that there is no alignment tolerance between the stop and the trench wall. An initial masking layer, through which the trench pattern is to be formed in a semiconductor island layer, is used as a doping mask for introducing a channel stop dopant into a surface portion of the semiconductor layer where the trench is to be formed. The lateral diffusion of the dopant beneath the oxide and adjacent to the trench aperture defines the eventual size of the channel stop. The semiconductor layer is then anisotropically etched to form a trench to a prescribed depth, usually intersecting the underlying semiconductor substrate. Because the etch goes through only a portion of the channel stop diffusion, leaving that portion which has laterally diffused beneath the oxide mask, the channel stop is self-aligned with the sidewall of the trench.

Abstract: A device accomplishes protection against breakdown of an N+ type diffused region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises N+ type substrate (1) over which there is superimposed an N- type epitaxial layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffused region (6). The diffused region (6) is insulated electrically with respect to the P type containment region (5).