Patents Examined by William David Coleman
  • Patent number: 10084011
    Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters comprises providing a substrate including a medium, a flow layer disposed on the medium, and a plurality of strained crystalline semiconductor islands having an initial lattice parameter arranged on the flow layer. The strained semiconductor islands are selectively treated so as to form a first group of strained islands having a first lateral expansion potential, and a second group of strained islands having a second lateral expansion potential that is different from the first lateral expansion potential. The substrate is heat treated at a temperature at or above a glass transition temperature of the flow layer to cause differentiated relaxation of the islands of the first and second groups, such that a lattice parameter of the first group of relaxed islands differs from a lattice parameter of the second group of relaxed islands.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 25, 2018
    Assignee: Soitec
    Inventors: David Sotta, Olivier Ledoux, Olivier Bonnin
  • Patent number: 7385220
    Abstract: Fibers having an electrically conductive outer surface and having an average diameter of less than about 5 millimeters; and a dielectric polymeric layer comprising a polymer having a main polymer chain on the outer surface, the dielectric polymeric layer having a thickness of less than about 50 microns, the main polymer chain comprising carbon. Fiber transistors having an on/off ratio of at least about 10. Techniques for making fibers and fiber transistors.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: June 10, 2008
    Assignee: Lucent Technologies Inc.
    Inventors: Jimmy Granstrom, Howard Edan Katz
  • Patent number: 7335527
    Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: February 26, 2008
    Inventors: William D. Sawyer, Jeffrey T. Borenstein
  • Patent number: 7274079
    Abstract: An accelerometer (305) for measuring seismic data. The accelerometer (305) includes an integrated vent hole for use during a vacuum sealing process and a balanced metal pattern for reducing cap wafer bowing. The accelerometer (305) also includes a top cap press frame recess (405) and a bottom cap press frame recess (420) for isolating bonding pressures to specified regions of the accelerometer (305). The accelerometer (305) is vacuum-sealed and includes a balanced metal pattern (730) to prevent degradation of the performance of the accelerometer (305). A dicing process is performed on the accelerometer (305) to isolate the electrical leads of the accelerometer (305). The accelerometer (305) further includes overshock protection bumpers (720) and patterned metal electrodes to reduce stiction during the operation of the accelerometer (305).
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: September 25, 2007
    Assignee: Input/Output, Inc.
    Inventors: Arjun Selvakumar, Howard D. Goldberg, Duli Yu, Matthew Ip, Martin A. Schmidt, James L. Marsh, Bing-Fai Fung, Philip Simon
  • Patent number: 7268032
    Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: September 11, 2007
    Assignee: Siliconix incorporated
    Inventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
  • Patent number: 7268033
    Abstract: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 7262130
    Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, copper typically requires use of a diffusion barrier to prevent it from contaminating other parts of an integrated circuit. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some advantages of using copper. Moreover, conventional methods of forming the copper wiring are costly and time consuming. Accordingly, the inventors devised one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7259026
    Abstract: There is provided a method and apparatus for processing an organosiloxane film, which allow an inter-level insulating film with a low dielectric constant to be formed at a low heat process temperature. A semiconductor (10) with a coating film formed thereon is loaded into a reaction tube (2) of a heat-processing apparatus (1). Then, the interior of the reaction tube (2) is stabilized at a predetermined pressure, and hydrogen is supplied into an inner tube (3) through an acidic gas feed line (13), to heat the coating film under an acidic atmosphere. Then, the interior of the reaction tube (2) is heated up to a predetermined temperature, while heating the coating film under an acidic atmosphere. Then, gas inside the reaction tube (2) is exhausted, and ammonia is supplied into the inner tube (3) through an alkaline gas feed line (14), to heat the coating film under an alkaline atmosphere.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: August 21, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Shingo Hishiya
  • Patent number: 7259032
    Abstract: A method for manufacturing an electronic device includes the steps of forming a first resist pattern on a primary surface of a SAW element, the first resist pattern having openings at positions corresponding to those at which bumps and a sealing frame are to be formed, sequentially forming metals over the first resist pattern, the metals being formed into adhesion layers, barrier metal layers, and solder layers, removing the first resist pattern on the SAW element such that the bumps and the sealing frame are simultaneously formed. When the bumps and the sealing frame of the SAW element are bonded to bond electrodes of the bond substrate, the solder layers are melted and alloyed by heating.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 21, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Murata, Takashi Iwamoto, Hiroki Horiguchi, Ryuichi Kubo, Hidetoshi Fujii, Naoko Aizawa
  • Patent number: 7256075
    Abstract: The invention relates to a method of transferring useful layers from a donor wafer which includes a multi-layer structure on the surface of the donor wafer that has a thickness sufficient to form multiple useful layers for subsequent detachment. The layers may be formed of materials having sufficiently different properties such that they may be selectively removed. The layers of material may also include sub-layers that can be selectively removed from each other.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: August 14, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Cécile Aulnette, Bénédite Osternaud, Takeshi Akatsu, Yves Mathieu Le Vaillant
  • Patent number: 7250310
    Abstract: In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical force. One aspect of the invention includes making use of specifically chosen adhesives to secure the die to the die paddle and to each other, so that any subsequent removal can readily be achieved.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Kevin Weaver, Chetan S. Paydenkar
  • Patent number: 7250671
    Abstract: Provided is a method for manufacturing a lead frame and a semiconductor package having a semiconductor chip for connecting to an outer board and having a base metal layer formed of iron and nickel as main elements. The method includes preparing the base metal layer of a lead frame, forming one or more plating layers on the base metal layer, mounting the semiconductor chip on the lead frame, molding the semiconductor chip and at least a portion of the lead frame, bending the lead frame to form the lead frame in a predetermined shape, and heat-treating the lead frame for forming a diffusion layer in order to protect the lead frame from corrosion.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 31, 2007
    Assignee: Samsung Techwin Co., Ltd.
    Inventors: Sang-hun Lee, Sung-kwan Paek, Se-chuel Park
  • Patent number: 7250350
    Abstract: An integrated circuit device structure (and methods). The structure includes a semiconductor substrate comprising a surface. A first doped polysilicon liner is defined within a first trench region formed on a first plug coupled to the surface of the substrate and a second doped polysilicon liner is defined within a second trench region on a second plug coupled to the surface of the substrate. The first trench region is separated from the second trench region by a predetermined dimension. The structure also has a first rugged polysilicon material overlying surfaces of the first doped polysilicon material within the first trench region and a second rugged polysilicon material overlying surfaces of the second doped polysilicon material in the second trench region. The first rugged polysilicon material is free from a possibility of electrical contact with the second rugged polysilicon material.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 31, 2007
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Liu Yong, Cui Yin
  • Patent number: 7247930
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a power management die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Patent number: 7247504
    Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Fujitsu Limited
    Inventors: Osamu Matsuura, Kenji Maruyama, Kazuaki Takai
  • Patent number: 7247879
    Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 24, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
  • Patent number: 7244657
    Abstract: The present invention provides a zeolite sol which can be formed into a porous film that can be thinned to an intended thickness by a method used in the ordinary semiconductor process, that excels in dielectric properties, adhesion, film consistency and mechanical strength, and that can be easily thinned; a composition for film formation; a porous film and a method for forming the same; and a high-performing and highly reliable semiconductor device which contains this porous film inside. More specifically, the zeolite sol is prepared by hydrolyzing and decomposing a silane compound expressed by a general formula: Si(OR1)4 (wherein R1 represents a straight-chain or branched alkyl group having 1 to 4 carbons, and when there is more than one R1, the R1s can be independent and the same as or different from each other) in a conventional coating solution for forming a porous film in the presence of a structure-directing agent and a basic catalyst; and then by heating the silane compound at a temperature of 75° C.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: July 17, 2007
    Assignee: Shin-Etsu Chemical Co. Ltd.
    Inventors: Tsutomu Ogihara, Fujio Yagihashi, Hideo Nakagawa, Masaru Sasago
  • Patent number: 7235419
    Abstract: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Steven T. Harshfield, David Q. Wright
  • Patent number: 7227247
    Abstract: In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Xiang Yin Zeng, Jiangqi He, BaoShu Xu
  • Patent number: 7223688
    Abstract: An apparatus including a volume of phase change material disposed between a first conductor and a second conductor on a substrate, and a plurality of electrodes coupled to the volume of phase change material and the first conductor. A method including introducing, over a first conductor on a substrate, a plurality of electrodes coupled to the first conductor, introducing a phase change material over the plurality of electrodes and in electrical communication with the plurality of electrodes, and introducing a second conductor over the phase change material and coupled to the phase change material.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: May 29, 2007
    Assignee: Ovonyx, Inc.
    Inventors: Tyler A. Lowrey, Manzur Gill