Abstract: The present invention is a method of producing semiconductor devices and an etching liquid with which the titanium nitride film can be removed without thinning of the CoSi layer. A hydrogen peroxide-water mixture is used for removal of the titanium nitride film in the method of producing semiconductor devices by cobalt salicide technology with titanium nitride as the cap film.

Abstract: Improved microelectromechanical systems (MEMS), processes and apparatus using thermocompression bonding are disclosed. For example, process embodiments are disclosed in which wafer-scale as well as die-scale thermocompression bonding is utilized to encapsulate MEMS and/or to provide electrical interconnections with MEMS. Apparatus embodiments include apparatus for performing thermocompression bonding and bonded hybrid structures manufactured in accordance with the process embodiments. Devices having various substrate bonding and/or sealing configurations variously offer the advantage of reduced size, higher manufacturing yields, reduced costs, improved reliability, improved compatibility with existing semiconductor manufacturing process and/or greater versatility of applications.

Abstract: An improved electronic packaging assembly is provided for increasing the operational bandwidth between different circuit devices, e.g. logic and memory chips, without requiring changes in current CMOS processing techniques. The electronic packaging assembly includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. The electronic packaging assembly also includes at least one, or a number of, semiconductor chips located on opposing surfaces of the silicon interposer. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. An optical detector and an optical emitter are located on the silicon interposer and couple the silicon interposer to a fiber optical network.

Abstract: A process for fabricating a microelectromechanical optical component from a silicon substrate is disclosed. The component comprises optical propagation guides; a wall which can move with respect to the propagation guides; and an electrostatic actuator associated with return means formed by at least one beam capable of causing the moving wall to move with respect to the rest of the substrate. The substrate is single-crystal silicon having (111) crystallographic planes parallel to the plane of the substrate. The process comprises a first series of deep reactive ion etching steps during which the heights of the moving wall, of the electrodes of the actuator, and of the beams of the return means of the actuator are defined with different values, and a second wet etching step, making it possible to free the moving wall, the electrodes and the beams from the rest of the substrate.

Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.

Abstract: A method of making an inductive transducer having inorganic nonferromagnetic material disposed in an apex region adjacent to a submicron nonferromagnetic gap in a magnetic core. The inorganic nonferromagnetic apex region can be made by chemical etching of a layer of inorganic nonferromagnetic material, deposition of inorganic nonferromagnetic material through a mask that is then lifted-off, or anisotropic etching of a layer of inorganic nonferromagnetic material that is covered by a hardbaked photoriesist mask.

Abstract: A high-quality diode is formed in an SOI process, using standard steps and implant doses that are used in the process for other devices such as a FET and a buried resistor; in particular using a buried resistor mask and implant to form one side of the diode, using the FET gate oxide to terminate the P-N junction, and using the FET gate to protect the junction from shorting during the silicide step.

Abstract: There is disclosed a semiconductor processing apparatus comprising a process chamber treating a substrate, a process gas feeder feeding a process gas to the process chamber, a first vacuum pump exhausting the process chamber, a second vacuum pump inhaling gas on an exhaust side of the first vacuum pump, and a circulation path circulating at least a part of the process gas exhausted from the process chamber via the first vacuum pump into the process chamber, wherein the circulation path is provided with a dust trapping mechanism, the dust trapping mechanism being capable of substantially maintaining a conductance of the circulation path before and after the capture of dust.

Abstract: An apparatus (10) for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling is disclosed. The apparatus (10) comprises a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically connected and mechanically bonded to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).

Abstract: A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to opposite sides of the gate electrodes. N-type impurities, preferably phosphorous atoms, are then implanted into the first source/drain region which will serve as the capacitor buried contact.

Abstract: A three axis MEM tunneling/capacitive sensor and method of making same. Cantilevered beam structures for at least two orthogonally arranged sensors and associated mating structures are defined on a first substrate or wafer, the at least two orthogonally arranged sensors having orthogonal directions of sensor sensitivity. A resonator structure of at least a third sensor is also defined, the third sensor being sensitive in a third direction orthogonal to the orthogonal directions of sensor sensitivity of the two orthogonally arranged sensors and the resonator structure having a mating structure thereon. Contact structures for at least two orthogonally arranged sensors are formed together with mating structures on a second substrate or wafer, the mating structures on the second substrate or wafer being of a complementary shape to the mating structures on the first substrate or wafer.

Abstract: An apparatus, system and method for the real-time monitoring of plasma charging during plasma processing are provided which overcome the deficiencies in currently available apparatus, systems and methods. According to one embodiment, the method and apparatus utilizes a detection wafer that comprises an Al pad located on the wafer and placed in contact with the plasma. The potential difference generated between the Al pad and a substrate as a result of plasma processing is the plasma charging voltage Vc. The potential difference is transmitted through electrical contacts located in a modified biased lift pin assembly supporting the detection wafer, and in the detection wafer itself, at locations remote from the plasma. Electrical contact with the detection wafer is thus established by positive physical contact from the biased lift pins and the potential difference is registered on apparatus external to the processing chamber and connected to the electrical contacts located remotely from the plasma.

Abstract: Compound semiconductor structures and devices can be grown on patterned oxide layers deposited on silicon. The deposition of Group II-VI and Group II-V compound semiconductors on patterned wafers results in an increase in the critical thickness for lattice mismatched layers and the relief of strain energy through side walls. As a result, high crystalline quality compound semiconductor material can be grown on less expensive and more accessible substrate to more cost effectively produce semiconductor components and devices having enhanced reliability.

Abstract: A manufacturing method of a thin film transistor (TFT) having low serial impedance is described. The method uses a back-side exposure and uses the active area as a hard mask; therefore, photomask usage may be reduced. On the other hand, a Si-Ge layer is used to react with the conductive layer deposited thereon after for forming a Ge-salicide layer. The method may reduce the required temperature of forming a Ge-salicide layer and the serial impedance.

Abstract: In the pattern of a selective growth mask for directly forming an active layer, open stripes for growing recombination layers to be inserted into a current blocking are formed in addition to an open stripe for growing the active layer. By this mask pattern, the position and band gap of the recombination layers are controlled. Whereby, at an arbitrary position in the vicinity of the active layer, recombination layers having an arbitrary band gap can be batch formed together with the active layer. Thus, a semiconductor laser element with an excellent high-temperature high-output characteristic can be fabricated with good uniformity and reproducibility.

Abstract: A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regio

Abstract: A method for crystallizing an amorphous silicon film which includes the steps of: preparing a substrate having the amorphous silicon film, the amorphous silicon film being formed on an intermediate layer in which an inner space exists; applying an energy to the amorphous silicon film in order to crystallize the amorphous silicon film, wherein the step of preparing the substrate includes the steps of: forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, forming the amorphous silicon film on the intermediate layer, selectively removing the amorphous silicon film and the intermediate layer to expose a part of the material layer for forming space, and removing the material layer for forming space; or forming a material layer for forming the space on an insulating substrate, forming the intermediate layer to cover the material layer, selectively removing the intermediate layer to expose a part of the material layer, removing the mate

Abstract: The present invention provides for an improvement of the interlayer adhesion property of the low-K layers in a dual damascene process. The method includes a shallow ion implantation process to bombard a bottom low-k layer for forming a densified layer on the bottom low-k layer. The densified layer can be a used as a substitute in the oxidation of the prior art to avoid the peeling phenomenon between the organic low-k layers.

Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.

Abstract: A semiconductor device comprises a first insulating film provided over a substrate and heat-treated, a second insulating film provided over the first insulating film, and a semiconductor film provided over the second insulating film, the second insulating film and the semiconductor film being formed successively without exposing them to the atmosphere.