Abstract: A multiprogramming data processing system comprises a plurality of data processing devices P1, P2, P3, P4 each having local storage 110-116 and has furthermore an interconnecting standard bus 100. The program is divided in program segments S1-S4, while the program segments are grouped into program portions (k, m, n). The respective program portions are each stored at one of the local memory sections. When an extended branch instruction calls an address in a different program portion, a portion change interrupt signal (26) is generated, whereby dynamical allocation of the execution of program segments may be realized. When a privileged portion (0) is called, the portion change interrupt is nullified, both at the calling to, (28) and the return (23) from the privileged program portion.

Abstract: A data processing system is disclosed which includes a memory having a plurality of addressable register banks and for memory areas for performing a re-entrant function of a subroutine. The memory areas store a start address of an interrupt program, a program status word of the interrupt program, and a register bank pointer code to be used by the interrupt program. The memory has a program counter, a program status word, and a register bank pointer. When an interrupt request is received, the contents of a program counter, the program status word, and the register bank pointer are swapped with the contents of a particular memory area group. Further, by swapping the contents of the program counter with the contents of the register in the register bank which contains in advance the start address of the subroutine to be used, the re-entrant operation of the subroutine may be accomplished.

Abstract: Disclosed is an improved system for verifying the spelling and providing hyphenation points for text words from a plurality of interspersed languages. The control system includes control codes which are inserted in the text to define the language of the text following the control code. The system accepts the control codes and responds by comparing the text following the control code against a storage dictionary of correctly spelled words and hyphenation points for the language associated with the control code. The system provides as an output an indicator of whether the word is correctly spelled or where the proper hyphenation points for the word appears. The systemn further includes control codes which when detected will cause blocks of data which should not be compared to the storage dictionary to be skipped.

Abstract: The processor of the present invention executes procedures, which comprise S-language instructions and names. S-languages are of higher order than typical machine languages and can be tailored to user high-order languages. Each procedure includes a dialect code which the processor interprets, enabling it to execute any of a plurality of dialects of S-languages. The processor includes means for resolving names into operand logical addresses. The processor possosses multiple levels of microcode control means, each with its own set of stacks.

Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.

Abstract: A display and control element is described which comprises several lighted push buttons which are--if necessary--mutually resetable and are mounted on a board insertable into a casing. The operating of the individual lighted push buttons as well as the optional mutual resetability is electrically determined by means of circuits. The arrangement and setting of such circuits is adjustable without change of the wiring by means of code switches, crossbar distributors, plug-in connectors, etc. or by means of the program (software) of a microprocessor which preferably is mounted on a separate plug-in board. For more complicated plants to be controlled several such elements may be combined in a casing and, if necessary, also several such casings may be connected to each other by means of data lines.

Abstract: A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

Abstract: A link (10) exchanges data between a master (MC) and slave (SC) computer. Each computer has control lines (26A, 42) and incompatible information lines (26B, 26C, CA1-15, CX1-21). The master computer (MC) includes a master interface (28) connected to the information and control lines (26) of the master computer (MC). The master interface (28) has separate intercommunication lines (LA/B) and intermediate (34) lines. This master interface (28) is able to provide an intermediate signal on its intermediate lines (34) in response to signals provided by the master computer (MC) on its control lines (26A). The link (10) includes a computing subsystem (30) and a slave interface (38). The computing subsystem (30) is connected to the intercommunication (LA/B) and intermediate (34) lines of the master interface (28). The computing subsystem (30) has command lines (36) for providing thereon a command signal in response to the intermediate signal.

Abstract: Address generating apparatus which uses narrow data paths for generating a wide logical address and which also provides for programs to access very large shared data structures outside their normally available addressing range and over an extended range of addresses. Selective indexed addressing is employed for providing index data which is also used for deriving variable dimension override data. During address generation, selected index data is added to a displacement provided by an instruction for deriving a dimension override value as well as an offset. The derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program. The resulting accessed address locating entry is in turn used to determine the particular portion of memory against which the offset is to be applied.

Abstract: A computer aided design system which results in reduced operator fatigue, increased speed, and increased accuracy features a single workspace for inputting information, such as type of drafting exercise, graphic element or symbol, element position established either by element coordinate designation or cursor tracking and alpha/numeric keyboard-like entries. The system utilizes dual CRT screens, one, the graphics screen, for viewing the end product of the graphic design and the other, the function screen, for providing a single workspace for entering data. In one embodiment, input data either in the form of fixed format blocks or sequentially presented menus are displayed to the operator at the function screen so that he may select appropriate inputs with a light pen. Because all types of inputs are accomplished at a single workspace, the single workspace function screen avoids eye and arm fatigue so that the operator (i.e.

Abstract: A data processing system intended for handling multiple tasks and comprising at least two processors, a memory unit and an I/O unit which are all connected to a data address and control signal transmission line. Each of the processors comprises an arithmetic-logic unit, a scratch pad memory, a processor status register, an interface, and a control unit which are all interconnected by a processor data bus. Each of the processors further contains an address interrupt unit whose input/output is connected to the data address and control signal transmission line. A first output of the address interrupt unit is connected to the processor data bus and its second output is connected to a second input of the control unit. A second control output of the control unit is connected to the input of the address interrupt unit. The invention helps increase the throughput of a data processing system and simplify the programming of interaction between the system's processors.

Abstract: An integrated circuit chip for controlling the transmission of data between a host peripheral device and other peripheral devices or a remote processor in which the transmission of data takes place in either a processor interrupt mode or a direct memory access mode. The integrated circuit chip includes first, second, third and fourth sequentially located edges forming a rectangle. The chip further includes input circuitry located generally adjacent the corner formed by the third and fourth edges and output circuitry located adjacent the first edge. A plurality of counters/registers associated with the input and output circuits are located adjacent the third edge. A Command register located adjacent the third edge selects the transfer mode and controls the operation of the integrated circuit chip in either an output or input mode. The chip may operate in a transmit only mode, receive only mode or transmit and receive modes simultaneously.

Abstract: This disclosure relates to a reduction processor for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.

Abstract: Operator keystrokes are processed in a text processor system to put characters and symbols on a fixed pitch display screen without limitation as to other size characters or symbols on the screen. Keystroke data is processed under the control of programs stored in a random access memory. For a mixed pitch display, the random access memory of the system is structured to include a text storage buffer and a display control block both interconnected to an applications program and a display access method program. Data is stored in the text storage buffer in an unformatted configuration in a mixed pitch arrangement and the programs evaluate the data to display characters and symbols with correct character pitch. The programs also draw a scale line on the screen to provide character information to the operator.

Abstract: An electronic digital processor system including a plurality of processing units with dedicated input port and output port for each of the processing units and an output port that is shared by the processing units. The digital processor system also includes a ROM for the storage of commands, a RAM for the storage of data, an arithmetic and logic unit for performing operations on the data, two independent and simultaneously operable processing units for executing these commands on the data and the control circuit for providing for simultaneous execution of commands in both processing units.

Abstract: A control system for interlocking processors in a multiprocessing organization. Each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors. The control system insures that all processors access the most up-to-date copy of memory information with a minimal performance impact. The design allows read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. The shared cache system dynamically detects and moves lines, which are both shared and changed, to the common shared cache and moves lines from the shared cache once sharing has ceased.

Abstract: A novel apparatus and method for micro-computer control of lubrication systems which utilizes a micro-computer that receives input signals from a lubrication station indicative of the level of lubricant, the pressure of the lubricant, the number of lube cycles and/or strokes of the machine or lubricating system which are furnished to the micro-computer that also receives inputs from program, monitor, system cycle and control switches and supplies output signals so as to actuate the lubricating system on a periodic predetermined base. In addition, the micro-computer produces fault signals so as to protect the machine or machines being lubricated in the event a fault occurs.

Abstract: A recording system is provided for a picture information file device having a keyboard, a 2-dimension scanning device, a magnetic tape device, a display device, and a microprocessor. When registering new picture information, a retrieval title to which a delete mark is attached is searched. The length of the picture information recorded at the position represented by this retrieval title is compared with the length of the new picture information to be recorded. If the new picture information to be recorded is shorter, the new picture information is recorded in the deleted picture information area. If the new picture information is longer, another retrieval title with a delete mark attached thereto is searched and the same comparison is made.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by squaring the audio waveform and measuring two successive time intervals occurring between three successive positive-going transitions and subtracting the resulting measurements. If the calculated difference is less than a predetermined amount, positive-going transitions of the waveform are selected as bit cell boundaries. If, on the other hand, the calculated difference is greater than the predetermined amount, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class addressing controls are modified to change the distribution of cache contained data more uniformly among the congruence classes in the cache (by comparison with conventional cache class distribution). The cache addressing controls change the congruence class address as a function of the state of a higher-order bit or field in any CPU requested address.