Abstract: An iconic-to-iconic low-level image processor is provided which comprises a lurality of identical sequential intermediate stages located between an input stage adapted to be connected to image sources such as analog or digital television cameras, ranging devices and conformal mapping arrays and an output stage adapted to be connected, e.g. to monitors, robot vision systems, iconic symbolic mapping devices and image processing computers. The intermediate stages are provided with forward pathway connections which afford sequential image processing as well as retrograde (feedback) pathway connections between adjacent stages in reverse sequence and within stage, recursive pathway connections for each stage. The stages each include neighborhood operators and image buffers and a number of operations are supported including neighborhood operations on images within each stage and between-stage operations on each pixel such as threshold, boolean and arithmetic operations, function mappings and the like.

Abstract: A high speed CPU/sequencer for use in a video game provides multi-channel binary output for display control purposes. The CPU/sequencer includes a macro-section that is user programmable with macro-instructions and a micro-section that is user programmable with micro-instructions. The CPU/sequencer is responsive to display information provided by a game microprocessor during a brief handshake period and carries out display computations independently of the game microprocessor, at higher speed, and using larger binary data words.

Abstract: Encoding-decoding apparatus having an internal data path for diagnostic use. The apparatus includes control apparatus for providing signals controlling operation of the encoding-decoding apparatus, an input device connected to a source of data to be encoded and a source of data to be decoded, an output device connected to a destination for the encoded data and a destination for the decoded data, and apparatus connected between the input device and the output and device for performing the encoding and decoding. A data path responsive to the control signals receives encoded data from the output device and provides it to the input device.

Abstract: The invention disclosed provides circuitry which is selectively operable either as an input point or as an output point in a programmable controller having multiple input and output points for exchanging signals between a central processing unit (CPU) of the controller and a process being controlled. Preferably, operation as an input point or as an output point is under control of the CPU. The invention includes a common input/output terminal for terminating both input and output devices; an input return terminal for terminating a return conductor from the input device; an output return terminal for terminating a return conductor from the output device; a preload resistor connected between the input/output terminal and the output return terminal so that a status signal is developed across the preload resistor indicating the status (generally, open or closed) of the input device; and an insulated gate transistor (IGT) connected between the input/output terminal and the input return terminal.

Abstract: A memory programmable controller of the multiprocessor type having both word and bit processors is disclosed. The controller has a data memory in which process images of the process being controlled are stored and a user program memory in which a control program is stored. In order to increase the rate at which commands are executed by the controller, means are employed by which the bit processor fetches commands from the user program memory at the same time that it is executing a prior command. Accordingly, two sequential commands are respectively executed and fetched simultaneously, thereby increasing the speed of the controller. Separate bus systems dedicated to the bit processor which enable the bit processor to access the user program memory and the data memory are employed.

Abstract: A data processing system having a host processor and an attached processor is disclosed. Each processor is capable of executing user programs under a different operating system and each processor is capable of accessing system memory but the host processor controls and performs all input and output operations for both processors. System memory is shared by the processors, therefore, only one processor is active on the bus system at any given time. Apparatus is disclosed for holding the host processor and starting the attached processor upon a command from the host and apparatus is disclosed for holding the attached processor and starting the host in the event of interrupt conditions, attempted access by the attached processor to protected areas of memory, or execution of an "out" instruction by the attached processor. Memory mapping apparatus which is under host control, but provides mapping for both the host and attached processors is shown.

Abstract: A data processing apparatus having a dataflow architecture includes an addressor module, an operational module and a memory module, and data to be processed is accompanied by a command and is applied to the respective module through a uni-directional bus. The addressor module and the operational module are integrated within a common hardware circuit having a feedback loop. A normal operation (an arithmetic and logic operation) is executed by the common hardware circuit by using only the uni-directional bus, while an address generating operation is executed by the common hardware circuit by using the uni-directional bus and the feedback loop.

Abstract: A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

Abstract: A microcomputer which is set to a power-save mode by an external signal or an output signal from an instruction decoder, and is provided with a flip-flop circuit which is set when microcomputer is set to a power-save mode and is reset upon receipt of an external interruption signal or reset signal, and sends forth a power-save output signal.

Abstract: The disclosure provides an embedded hardware/software monitor for a data processing system. It embeds and distributes a plurality of instrumentation table units (ITUs) within various hardware entities in the system to collect sampled hardware signals local in the hardware entity in which the respective ITU is embedded, e.g. in each CPU, I/O processor, system controller, main storage controller, etc. Instrumentation measurement is controlled centrally in the system. Sampling of the system signals is done periodically at a low-rate relative to the CPU machine cycle rate, and the sampled signal are collected in the ITUs for instrumentation analysis. Sampling pulses are synchronously provided in all ITUs in the system. The ITU collected hardware signals are related to software controlled trace entries made in a trace table (TT) in main storage by each CPU in the system executing tracing and other predetermined instructions.

Abstract: A maintenance exerciser makes requests of certain inoperative and malfunctioning storage memory bank portions of a large scale storage memory unit concurrently that normal system requestors do request of remaining, correctly functional, storage memory bank portions of such storage memory unit. All requests are collectively prioritized in a priority network which, save for the circuit of the present invention, will not advance to successive prioritizations until each currently prioritized request is positively acknowledged by the requested storage memory bank.

Abstract: A management communication terminal is formed by integrating an electronic, raster scanning camera with a personal computer. The terminal has a keyboard, a Winchester disk drive, a telecommunication controller, a cathode ray tube monitor, and a thermographic, raster image printer. Two such terminals define an office information system for the exchange of information produced at the keyboards and by the cameras. In each terminal, the coded data generated at the keyboard and the raster image data generated by the camera are temporarily stored in separate data buffers and from there are routed to the monitor, the printer and disk storage. The monitor and printer are able to display and print respectively, images created from the keyboard data, the camera data or a combination of the two. The camera data is compressed prior to storage and is reduced in resolution prior to application to the monitor.

Abstract: A two-level controller for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities. The two-level controller is formed of a hierarchy of two control stores wherein the receipt of a command code by the first control store from the processor causes it to address the second control store. Each control store is provided with program counter means to receive its respective address and to increment that address until it receives a new address so as to asynchronously control simultaneous operation of a memory interface to said memory modules and a cache mechanism coupled to the processor.

Abstract: In a data processing system having linked lists it is useful to be able to add and delete items from such lists while maintaining the integrity of the linked nature of such lists. A new compare and swap instruction provides for effectively simultaneously swapping 2 values which is useful for safely adding and deleting items from linked lists. Prior to the instruction the status of the two value are read at the locations to be swapped. During the instruction these locations are checked again to ensure that no change has occurred at these locations before the instruction performs the swap of the two new values. The instruction then performs the proposed 2 value swap but only if no change has occurred at these two locations where the swap is to be performed.

Abstract: This disclosure improves data processing system integrity by assigning content types to virtual pages and using the assigned content types to enforce special access rules. The page content types are: (a) any changeable data and/or any executable instructions (current S/370); (b) SCP executable instructions and/or unchangeable data (SENC); (c) SCP restrictively changeable data only (system DO); and optionally (d) application data only (user DO). Page content type designation is done by providing in each PTE two integrity control flag bits called herein SENC and DO. In the first embodiment, the SENC and DO bits are separately coded to respectively control access to SENC and system DO page types. In a second embodiment the SENC and DO bits are combinatorially encoded to obtain four types. A new system integrity state, the SCP state, is provided to protect SENC and system DO page usage. The SCP state is initiated by a hardware interrupt, i.e.

Abstract: A virtual address and access protection code stored at that address are fetched simultaneously from secondary memory and stored in corresponding locations in first and second content addressable memories. When a program-generated virtual address is later applied to the first content addressable memory, corresponding access code is simultaneously applied to the second content addressable memory. Match signals obtained simultaneously from corresponding locations in both content addressable memories are combined to produce an access control signal to control access to data stored at a real memory address corresponding to the matched virtual address.

Abstract: Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data processing system which is operative in response to instructions having operation codes for specifying operations to be executed. The instructions also have operand fields for identifying operands to be utilized in connection with executing the instructions.

Abstract: In an electronic system, such as a digital data processing system, comprising a number of circuit boards, each circuit board being of a particular functional type and also uniquely identifiable by a manufacturing revision number, there is provided a status detection circuit for polling various programmable status information from the board, including a unique board identity number and the manufacturing revision number. The status detection circuit includes a microcomputer (60, FIG. 2) on each board 50. The data inputs of the microcomputer are responsive to a unique combination of switches (e.g., 42) representative of the manufacturing revision number. Other microcomputer inputs are responsive to a unique combination of edge connectors (e.g., 47) for uniquely identifying the particular board in the system. Another microcomputer input is responsive to an on-board status indicator, such as an LED.

Abstract: Disclosed is a demand paging scheme for a shared memory processing system that uses paged virtual memory addressing and includes a plurality of address translation buffers (ATBs). Page frames of main memory that hold pages being considered for swapping from memory are sequestered and flags, one corresponding to each ATB in the system, are cleared. Each time an ATB is flushed, its associated flag is set. Setting of all the flags indicates that the address translation information of pages held by selected sequestered page frames does not appear in any ATB and that the selected pages may be swapped from main memory.

Abstract: Incoming data messages to a system having a plurality of channels are assigned for processing to one of the channels to share the processing load more or less equally among all the channels of the system. Each channel receives messages by means of a communications link for processing. Included in each channel is a disk drive for a storage medium, a disk controller and peripheral controllers for input/output equipment as required. Each channel of the system also includes a data processor. A message is received from the communication link of any of the channels, which message is identified by the data processor of that channel. The processor then evaluates the number of messages waiting to be processed in each of the other channels for assignment to a channel having the least number of messages on the processing list. The processor considers only on-line channels in this assignment selection.