Abstract: A test system memory architecture for passing parameters and testing dynamic components includes a main memory 15, a mask memory 20, and a definition memory 25, operating under control of a main sequence control memory 18. A corresponding subroutine memory 38, subroutine mask memory 22, and subroutine definition memory 27 operate under control of a subroutine sequence control memory 33. Multiplexing apparatus is used to selectively connect any of these memories to the formatter circuit 10. In addition, the architecture includes a parameter enabling memory 30 which is coupled to the subroutine SCM 33 and a switching means for controlling which of the subroutine memory 38 or main memory 15 is coupled to the formatter circuit 10.

Abstract: A numerical control system in which a numerical control device is adapted to control a machine tool equipped with a plurality of tables, as one example, on which workpieces may be secured to be machined by a tool mounted on a head. A table which is not being controlled automatically by the numerical control device can be operated independently of the automatic operation network of the numerical control device and placed in a manual operation mode or manual data input mode in which the table can be moved manually even while the numerical control device controls the other table or tables automatically.

Abstract: Apparatus for regulating access by each of a plurality of asynchronous data processors to each of a plurality of memories, each processor being associated with one of the memories and needing both read and write access to its own memory and to the processor's memories, the apparatus including local bus circuitry to selectably permit each processor to have, or to prevent each processor from having, access to its associated memory, connecting bus circuitry to selectably permit each processor to have, or to prevent each processor from having, direct access to the other processors' memories, and control circuitry for giving each requesting processor access over the connecting bus to another processor's memory, and for giving each processor access over the local bus circuitry to its own memory except when access to its own memory is being given to another one of the processors.

Abstract: Data transfers between remote data sets, data terminals and a main host computer are controlled by a peripheral-controller designated as a Line Support Processor (LSP). The LSP manages a plurality of line adapters, each of which handles a separate data comm line. The LSP includes internal processor means and interface circuit means to effectuate data transfer operations using a variety of protocols and systems both for bit-oriented and byte-oriented data transfers.

Abstract: In an associative processor particularly useful for tomographic image reconstruction, the associative memory is partitioned into an array of associative processors concurrently performing the same function with different operands on disjoint data sets. The array is dynamically reconfigurable, and the partitioning is completely flexible, with individual processors free to assume any size and topology.While the new associative processor is of broad application, its power is specifically demonstrated for tomographic image reconstruction by the well-known convolution-back-projection method.

Abstract: In a data processing system of the type having a processor and a plurality of memory units, which can be accessed simultaneously by the processor, the processor writes simultaneously into both memory units and reads from a particular one of the memory units except when the particular memory unit exhibits an error condition in which case writing and reading are performed in a different memory unit. The switching from the master memory unit to an alternate memory is performed simultaneously with the error indication in the master memory unit during a write operation and is performed at the next clock pulse in a read operation so that a retry can be performed.

Abstract: A PLA (e.g., 100) operates with two-level clock control timing, that is, with a pair of master and slave registers (e.g., 12 and 13) connected to the PLA wordlines (e.g., W.sub.1, W.sub.2, . . . W.sub.n) between the PLA's AND and OR planes (e.g., 11 and 14). The slave register's output to the OR plane is controlled by a combinational logic device (e.g., 21), such as an AND gate to which a WAIT signal is applied. In this way, when the WAIT signal (e.g., W) is available at the beginning of a given cycle of the clock control timing, the output of the PLA (including PLA feedback) can respond to this WAIT signal before the end of the given cycle--that is, the PLA is capable of same-cycle decision making.

Abstract: A combinational logic device, such as an AND gate, is connected to control the flow of information along a wordline from the AND plane to the OR plane of a PLA (programmed logic array). To each such combinational logic device is applied an input signal from a source external to the PLA, so that the PLA's output can respond relatively quickly to this input signal--that is, the PLA is capable of relatively quick decision making.

Abstract: An intelligent asynchronous controller (IAC) for use in operably coupling a plurality of asynchronous input/output (I/O) devices to a host central processing unit (CPU) is disclosed. The IAC is designed and programmed to control the transfer of data between the plurality of I/O devices and the CPU, to perform character processing on the data received from the I/O devices before transmission to the host CPU and to perform other types of data processing.

Abstract: Signal processor device having a processor module and a conditional interrupt module for use in a multiprocessor system employing these signal processor devices. The processor module has address, data and control inputs and outputs, including an interrupt signal input for receiving an incoming interrupt request signal. The signal processor device has at least one conditional interrupt module in which the identity address of the signal processor is present, said interrupt module having inputs for receiving an incoming external interrupt request signal with corresponding destination address. The conditional interrupt module also has comparators in which its identity address is compared with the destination address. If the addresses agree, an interrupt signal is fed to the interrupt signal input of the processor module. The processor module may also have an interrupt signal output and be provided with an arbitration module to prevent conflicts between several interrupt requests.

Abstract: A method for use with a computer which directly transfers incoming data into the computer memory. A functional address contained in a received message is used to index a pointer in a vector table. The indexed pointer addresses an input control block associated with the functional address. The input control block is used to control the flow of data into the computer memory. The input control block also controls access to the computer memory for subsequent messages having the same functional address.

Abstract: Disclosed is a conductivity detector for use in chromatography systems. The improved conductivity detector provides digital processing of a conductivity signal to provide improved stability. The detector compares a trial offset signal with a detected conductivity signal and when the compared values are within a predetermined value the detector processes the compared value and the final offset value thereby providing improved accuracy with higher resolution.

Abstract: An interactive terminal data processing system includes a number of work stations, all coupled in common to a single conductor coaxial bus which may be up to one kilometer in length. Work stations may be connected to the bus by up to a ten foot coaxial cable with the connection to the bus being typically no less than thirty feet apart.

Abstract: A buffered cache memory subsystem is disclosed which features a solid-state cache memory connected to a storage director which interfaces a host channel with a control module controlling operation of a long-term data storage device such as a disk drive. The solid-state cache memory is connected to plural directors which in turn may be connected to differing types of control modules, whereby the cache is usable with more than one type of long-term data storage means within a given system. The cache memory may be field-installed in a preexisting disk drive storage system and is software transparent to the host computer, while providing improvements in overall operating efficiency. In a preferred embodiment, data is only cached when it is expected to be the subject of a future host request.

Abstract: An arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made. A one indicates that the request was made by the module in which the FIFO is located, and a zero indicates that the request was made by one of a number of other similar modules. The request status information from the other modules is received over signal lines (411) connected between the modules. This logic separates multiple requests into time-ordered slots, such that all requests in a particular time slot may be serviced before any requests in the next time slot. A store (409) stores a unique logical module number. An arbiter (410) examines this logical number bit-by-bit in successive cycles and places a one in a grant queue (412) upon the condition that the bit examined in a particular cycle is a zero and signals this condition over the signal lines.

Abstract: A mechanism for a data processor that is adapted to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately and concurrently executed by a plurality of processing elements. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by converting the audio waveform into a square wave and examining the square wave for predetermined pulse patterns. If one pattern is found, the positive-going edge of the waveform is selected as the bit cell boundary. If, on the other hand, another pattern is found, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: A data processor having a plurality of processing elements and a mechanism to receive strings of object code, form them into higher level tasks and to determine sequences of such tasks which are logically independent so that they may be separately and concurrently executed by the plurality of processing elements. The mechanism makes all memory accesses required by the various tasks and stores those tasks along with corresponding pointers or references to local memory in which the various data items have now been stored. The mechanism employs a symbol translation table in which the tasks are stored in forms of queues along with symbols representing the various references or pointers to local memory. In this manner, various data items can be assigned different symbols or symbolic names for use with different tasks thus further limiting dependency between various tasks and controlling data changes.

Abstract: The disclosure describes a novel cache directory entry replacement method and means for central processors (CPs) in a multiprocessor (MP) based on task identifiers (TIDs) provided in each directory entry to identify the program task which inserted the respective entry. A remote TID register is provided to receive the TID from any remote CP in the MP on each cache miss cross-interrogation hit from any remote CP. Each time a respective CP (i.e. local CP) makes a storage request to its private cache directory, a congruence class in the directory is selected and the TIDs in the selected class are compared to any remote TID in the CP's remote TID register. A TID candidate is any entry in the class which compares equal to the remote TID and is not equal to the current local processor TID. It is identified as a candidate for replacement in the local cache directory on a cache miss.

Abstract: A system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction; and a clock generator supplied with the output of an oscillator for developing a basic clock of a desired waveform for supply to the system, wherein the basic clock is developed or inhibited when the control signal is supplied from the clock control signal generator.