Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

Abstract: A given planarity of the underlying layer is ensured after removal of a porous layer. In the first step, a porous layer is filled with a preprocess solution (e.g., water). In the second step, the preprocess solution filling the porous layer is replaced with an etchant (e.g., fluoric acid), and the porous layer is etched by the etchant. With this process, the time in which the porous layer is filled with the etchant is shortened to suppress variations in progress of etching.

Abstract: A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method of manufacturing semiconductor devices using an improved planarization processes for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable coating.

Abstract: Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material.

Abstract: The polishing slurry includes polishing particles having a mean particle diameter of less than about 5 &mgr;m. The slurry contains at least about 0.5 weight percent oxidizer selected from at least one of the group consisting of HNO3, Ni(NO3)2, Al(NO3)3, Mg(NO3)2, Zn(NO3)2 and NH4NO3. A small but effective amount of a co-oxidizer selected from the group consisting of perbromates, perchlorates, periodates, persulfates, permanganates and ferric nitrate accelerates removal of substrates; and water forms the balance of the aqueous slurry.

Abstract: SOI substrates are fabricated with sufficient quality and with good reproducibility. At the same time, conservation of resources and reduction of cost are realized by reuse of the wafer and the like. Carried out to achieve the above are a step of bonding a principal surface of a first substrate to a principal surface of a second substrate, the first substrate being Si substrate in which at least one layer of non-porous thin film is formed through a porous Si layer, a step of exposing the porous Si layer in a side surface of a bonding substrate comprised of the first substrate and the second substrate, a step of dividing the porous Si layer by oxidizing the bonding substrate, and a step of removing the porous Si and oxidized porous Si layer on the second substrate separated by the division of the porous Si layer.

Abstract: A plasma processing apparatus mainly comprises a processing chamber (10) formed by a vacuum vessel, a magnetic field forming coil (80) arranged around the processing chamber for forming a rotating magnetic field and gas supply means (101) supplying various gases to the processing chamber (10). The processing chamber (10) is divided into a reaction chamber (44) forming plasma with a partition wall (43) and a buffer chamber (45) discharging externally supplied gases with pressure difference. The reaction chamber (44) includes a high-frequency electrode arranged oppositely to the buffer chamber (45). The gas supply means (101) includes pulse gas valves (63a and 63b) for pulsatively supplying gases to the processing chamber (10). Thus provided are a plasma processing method and a plasma processing apparatus capable of uniformly processing a wafer having a large diameter and reducing RIE lag with respect to a fine etching pattern.

Abstract: As a bottom anti-reflective coating material for use in photolithography, polymer dyes represented by following general formula are used. The polymer dyes are able to form a bottom anti-reflective coating having good film formation properties, good absorption properties at exposure wavelength, good step coverage, non-intermixing with photoresist and high etch rate. wherein R represents H or a substituted or non-substituted alkyl, cycloalkyl, or aryl group, R1 represents a substituted or non-substituted alkyl or aryl, or a —COOR3 group in which R3 represents an alkyl group, R2 represents a substituted or non-substituted alkyl, cycloalkyl, or aryl group, D is an organic chromophore which absorbs at the exposure wavelength (150-450 nm) and represents a substituted or non-substituted aryl, condensed aryl, or heteroaryl group, m and o are any integer above zero, and n, p and q are any integer including zero.

Abstract: A method for fabricating stacked vias for microelectronic components. The method has a first step of providing a first patterned interconnect layer on a substrate. A first insulating layer is then applied on the first interconnect layer. A first via is formed in the first insulating layer and is in contact with the first interconnect layer. A second patterned interconnect layer is applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is then deposited on the second interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer in such a way that it meets the first via directly.

Abstract: A method of removing Chemical Mechanical Polishing (CMP) residue from a semiconductor substrate is disclosed. The semiconductor substrate with the CMP residue on a surface is placed within a pressure chamber. The pressure chamber is then pressurized. Supercritical carbon dioxide and a solvent are introduced into the pressure chamber. The supercritical carbon dioxide and the chemical are maintained in contact with the semiconductor substrate until the CMP residue is removed from the semiconductor substrate. The pressure chamber is then flushed and vented.

Abstract: A method and apparatus for etching of a substrate comprising both a polysilicon layer and an overlying tungsten layer. The method comprises etching the tungsten layer in a chamber using a plasma formed from a gas mixture comprising a fluorinated gas (such as CF4, NF3, SF6, and the like) and oxygen.

Abstract: A centrifugal spray processor for dispensing a stream of ozonated water toward one or more semiconductor wafers at a non-parallel angle that is inclined from the plane of the surface of the semiconductor wafer. The spray processor includes one or more supports for receiving a plurality of semiconductor wafers and a spray post for dispensing ozonated water from a reservoir onto the semiconductor wafers. The spray post includes a plurality of nozzles that are configured to dispense ozonated water at a generally downward angle toward the surface of the semiconductor wafer. The angle of incidence of the stream of ozonated water from the spray post as measured from the plane of the semiconductor is greater than 0 degrees, and is preferably greater than about 0 degrees and less than or equal to about 30 degrees depending upon the configuration of the spray post and the semiconductor wafers.

Abstract: By locally heating or cooling a substrate in an etching process, temperature unevenness is controlled, and convection currents of an etching liquid are restricted simultaneously. By setting the etching temperature low in an initial stage of the etching process and increasing it in a final stage, uniform and quick etching is possible. In a drop etching method, generation of bubbles can be prevented to ensure uniform etching by providing gas release openings in a member opposed to the substrate.

Abstract: In one aspect, the present invention provides crystallization solutions useful for crystallizing proteins and other molecules, especially macromolecules. In a presently preferred embodiment, the crystallization solutions of the invention are combined as four crystallization solution sets. Each of the four crystallization solution sets includes forty eight different crystallization solutions. Each individual crystallization solution includes a precipitant and a buffer, and optionally includes at least one additive. In another aspect, the present invention provides kits including a plurality of crystallization solutions of the present invention and at least one crystallization plate that preferably includes a plurality of reservoirs. Preferably the crystallization solutions are disposed within the reservoirs of the crystallization plates.

Abstract: A computer implemented method for endpointing an etch process comprising the acts of monitoring an attribute of a pressure control valve and determining an endpoint of the process based upon the monitored attribute. The monitored attribute includes the position of the pressure control valve or the rate of change of the pressure control valve. The method is advantageously employed in an in-situ cleaning process of a polymerized plasma chamber.

Abstract: A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dual damascene stacked conductor interconnection layer. There is provided a substrate employed within a microelectronics fabrication wherein a series of conductor regions comprising a microelectronics conductor layer is formed within the substrate. There is then formed over the substrate a first dielectric layer. There is then formed over the first dielectric layer an intermediate low dielectric constant dielectric layer. There is then formed over the intermediate low dielectric constant dielectric layer a second dielectric layer. There is then formed over the second dielectric layer a first patterned photoresist etch mask layer, which is a contact via hole pattern. There is then etched the pattern of the first photoresist etch mask layer through the dielectric layers, employing a first anisotropic reactive etch process. There is then stripped the first patterned photoresist etch mask layer.

Abstract: A method of etching an electrode layer (e.g., a platinum electrode layer or an iridium electrode layer) disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 &mgr;m and having a profile equal to or greater than about 85°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising oxygen and/or chlorine, argon and a gas selected from the group consisting of BCl3, HBr, HCl and mixtures thereof. A semiconductor device having a substrate and a plurality of electrodes supported by the substrate. The electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 &mgr;m and a profile equal to or greater than about 85°.