Patents Examined by William Powell
  • Patent number: 6602432
    Abstract: A high-speed operation of an electroabsorption modulator is intended. A p-InGaAs contact layer 9 is formed not only in an optical modulation region MA but also in an optical coupling region CA, and an AlInAs oxide layer 7 is disposed in p-InP cladding layers 5 and 8 in a mesa MS portion of the optical coupling region CA.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: August 5, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takayuki Matsuyama
  • Patent number: 6602428
    Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: August 5, 2003
    Assignee: Denso Corporation
    Inventors: Hiroyuki Wado, Makiko Sugiura, Toshimasa Yamamoto, Yukihiro Takeuchi, Yasushi Kohno
  • Patent number: 6602433
    Abstract: A substrate is treated by supplying an etchant and/or deposition gas into a chamber in which the substrate is situated. In order to avoid the problems associated with transportation of toxic gases, the gases required for such processes are delivered directly from a gas generation and delivery system positioned locally to the chamber.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: August 5, 2003
    Assignee: Surface Technology Systems PLC
    Inventors: Jyoti Kiron Bhardwaj, Nicholas Shepherd, Leslie Michael Lea
  • Patent number: 6602383
    Abstract: An apparatus for use in processing a workpiece to fabricate a microelectronic component is set forth. The apparatus comprises a process container having a process fluid therein for processing the workpiece and a workpiece holder configured to hold the workpiece. A position sensor is employed to provide position information indicative of the spacing between a surface of the workpiece and a surface of the process fluid. A drive system provides relative movement between the surface of the workpiece and the surface of the process fluid in response to the position information. Preferably, the relative movement provided by the drive system comprises a first motion that causes the surface of the workpiece to contact the surface of the process fluid, and a second motion opposite the direction all of and following the first to generate and maintain a column of process fluid between the surface of the process fluid and the surface of the workpiece.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: August 5, 2003
    Assignee: Semitool, Inc.
    Inventors: Robert W. Batz, Jr., Reed A. Blackburn, Steven E. Kelly, James W. Doolittle
  • Patent number: 6599435
    Abstract: A gas at an extremely low temperature is jet-sprayed onto a warped concave surface of a wafer to correct this warped concave surface flat.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: July 29, 2003
    Assignee: TDK Corporation
    Inventors: Toshio Kubota, Fujimi Kimura
  • Patent number: 6599436
    Abstract: A method is disclosed to form external interconnections to a microfluidic device for coupling of a fluid or light or both into a microchannel of the device. This method can be used to form optical or fluidic interconnections to microchannels previously formed on a substrate, or to form both the interconnections and microchannels during the same process steps. The optical and fluidic interconnections are formed parallel to the plane of the substrate, and are fluid tight.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: July 29, 2003
    Assignee: Sandia Corporation
    Inventors: Carolyn M. Matzke, Carol I. H. Ashby, Leonardo Griego
  • Patent number: 6599840
    Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
  • Patent number: 6599836
    Abstract: Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical planarizing processes. In one aspect of the invention, a microelectronic-device substrate assembly is planarized by abrading material from the substrate assembly using a plurality of first abrasive particles and removing material from the substrate assembly using a plurality second abrasive particles. The first abrasive particles have a first planarizing attribute, and the second abrasive particles have a second planarizing attribute. The first and second planarizing attributes are different from one another to preferably selectively remove topographical features from substrate assembly and/or selectively remove different types of material at the substrate surface.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Karl M. Robinson, Scott G. Meikle
  • Patent number: 6596642
    Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: July 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
  • Patent number: 6596186
    Abstract: A mask for a selective growth of a solid, is provided in which the solid is selectively grown in a predetermined region of a substrate and growth on other regions is suppressed. A method is also provided for selectively growing a solid on only the predetermined region of a substrate using the mask. In the mask, a surface layer and an underlayer are provided, each having different chemical compositions. Thus, even if the mask is formed on a substrate in an ultra thin film, the generation of mask defects can be suppressed and stability provided to heat and electron beams.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: July 22, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tetsuji Yasuda, Kazuyuki Ikuta, Satoshi Yamasaki, Kazunobu Tanaka, Doo-sup Hwang
  • Patent number: 6596648
    Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: July 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
  • Patent number: 6589385
    Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: July 8, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Akiyuki Minami, Satoshi Machida
  • Patent number: 6589434
    Abstract: The present invention relates to an exposure apparatus and a method for manufacturing 3-D horn antenna using the exposure apparatus. More particularly, it relates to a method for manufacturing a horn-shaped 3-D micro-structure antenna and an extremely low-speed, inclined-rotating, parallel exposure apparatus that makes it possible to manufacture the 3-D micro-structure antenna mentioned above.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: July 8, 2003
    Assignee: Institute of Science and Technology
    Inventors: Sung Moon, Jong Yeon Park
  • Patent number: 6586262
    Abstract: The present invention is a method for end point detection where emission spectra are detected during etching of an object to be processed, such as a semiconductor wafer, by a spectrometer, and an end point of the etching is detected, comprising performing etching of a sample, corresponding to a product, prior to etching of a semiconductor wafer which is the product, sequentially measuring full-spectra of plasma, performing principal component analysis of the emission spectra using the emission intensities of all wavelengths of each of the full-spectra, holding the results as data, thereafter obtaining a principal component score for each of the full-spectra sequentially measured during etching of a semiconductor wafer to be manufactured on the basis of the emission intensities of all the wavelengths, and then detecting an end point of etching on the basis of a substantial change of the principal component score for each of the full-spectra sequentially measured.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: July 1, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Susumu Saito, Shinji Sakano
  • Patent number: 6586342
    Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems apply liquid etchant in a precise manner at the edge bevel region of the wafer under viscous flow conditions, so that the etchant is applied on to the front edge area and flows over the side edge and onto the back edge in a viscous manner. The etchant thus does not flow or splatter onto the active circuit region of the wafer. An edge bevel removal embodiment involving that is particularly effective at obviating streaking, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: July 1, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Seshasayee Varadarajan, Andrew J. McCutcheon
  • Patent number: 6586336
    Abstract: A small footprint, integrated and automated semiconductor wafer processing system for planarizing semiconductor wafers. That processing system includes a wafer load station, at least one CMP polishing system, and at least one cleaning system. Also included is at least one wafer unload station and a robotic system. The robotic system, which includes from two to six robotic movers, moves semiconductor wafers through the semiconductor wafer processing system. The semiconductor wafer processing system can also include a buffer system for temporarily holding semiconductor wafers. The buffer system, the robotic system, the cleaning system, the wafer load station, and/or the wafer unload station in some applications are capable of Z-axis motion. CMP polishing systems and cleaning systems can be vertically or linearly stacked.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: July 1, 2003
    Assignee: Oriol, Inc.
    Inventor: In Kwon Jeong
  • Patent number: 6585905
    Abstract: A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads. An overmold covers the semiconductor die and all except one surface of the at least one row of contact pads and the die attach pad.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: July 1, 2003
    Assignee: ASAT Ltd.
    Inventors: Chun Ho Fan, Tsui Yee Lin, Kin Yan Tsang, Neil McLellan
  • Patent number: 6585908
    Abstract: A process and apparatus for determining a real-time etching rate during a plasma mediated etching process. Real-time etching rate determination includes monitoring an interference pattern generated by a direct light beam and a reflected light beam from a wafer surface. A viewing angle for recording the interference pattern is nearly parallel to the wafer plane and at a fixed focal point on the layer to be removed. The direct light beam and reflected light beams are generated in situ during plasma processing.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: July 1, 2003
    Assignee: Axcelis Technologies, Inc.
    Inventors: Andre G. Cardoso, Alan C. Janos
  • Patent number: 6585909
    Abstract: An oxide for use in a bolometer with an oxide thin-film formed is manufactured on an insulating substrate. Metal organic compound is dissolved in solvent to form solution during manufacturing the oxide thin-film. The solution is applied on the insulating substrate, and the applied solution is dried. A bond between carbon and oxygen is cut and decomposed by irradiating a laser ray with wavelength of 400 nm or less. A generated oxide is crystallized.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: July 1, 2003
    Assignees: National Institute of Advanced Industrial Science & Technology, NEC Corporation
    Inventors: Tetsuo Tsuchiya, Susumu Mizuta, Toshiya Kumagai, Tsutomu Yoshitake, Yuichi Shimakawa, Yoshimi Kubo
  • Patent number: 6583067
    Abstract: The present invention is a method to avoid deterioration of a dielectric characteristic of a dielectric layer having a low dielectric constant (low k) during a stripping process. The method involves first forming a low k dielectric layer on the surface of a substrate of a semiconductor wafer. Then, a patterned photoresist layer is formed over the surface of the low k dielectric layer. The patterned photoresist layer is then used as a hard mask to perform an etching process on the low k dielectric layer. A stripping process is then performed to remove the patterned photoresist layer. Finally, a surface treatment is utilized on the low k dielectric layer to remove Si—OH bonds in the low k dielectric layer so as to avoid moisture absorption of the low k dielectric layer that causes deterioration of the dielectric characteristic.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: June 24, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Ting-Chang Chang, Po-Tsun Liu, Yi-Shien Mor