Patents Examined by Wilner Jean Baptiste
  • Patent number: 11398414
    Abstract: Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Chia-Pin Chiu, Pooya Tadayon, Joe F. Walczyk, Chandra Mohan Jha, Weihua Tang, Shrenik Kothari, Shankar Devasenathipathy
  • Patent number: 11398441
    Abstract: The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 11398447
    Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 26, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shohei Ogawa, Junji Fujino, Satoru Ishikawa, Takumi Shigemoto, Yusuke Ishiyama
  • Patent number: 11398446
    Abstract: A die attachment material may include an ultra-violet (UV) curable resin and silver particles to attach a chip to a submount, where the silver particles are positioned within the UV curable resin. A method may include heating the die attachment material to obtain the UV curable resin on sintered silver particles, where at least a portion of the die attachment material is position between a chip and a submount. The method may further include irradiating, with UV light, the UV curable resin to obtain a polymer on the sintered silver particles. The polymer may form a layer on the sintered silver particles.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: July 26, 2022
    Assignee: Lumentum Operations LLC
    Inventors: Zhengwei Shi, Lijun Zhu, Jihua Du
  • Patent number: 11393788
    Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Mao Guo, Hyoung Il Kim, Yong She, Sireesha Gogineni
  • Patent number: 11387203
    Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: July 12, 2022
    Assignee: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung Ho, Chi-Hsueh Li
  • Patent number: 11387201
    Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 12, 2022
    Assignee: XINTEC INC.
    Inventors: Po-Han Lee, Chia-Ming Cheng, Jiun-Yen Lai, Ming-Chung Chung, Wei-Luen Suen
  • Patent number: 11387225
    Abstract: A fan-out type semiconductor package may include a frame, an upper chip stack, a first redistribution pattern, a lower chip stack, a second redistribution pattern and a redistribution post. The frame may have a cavity. The upper chip stack may be arranged in the cavity. The first redistribution pattern may be arranged under the frame. The first redistribution pattern may be electrically connected with the upper chip stack. The lower chip stack may be arranged under the first redistribution pattern. The second redistribution pattern may be arranged under the lower chip stack. The second redistribution pattern may be electrically connected with the lower chip stack. The redistribution post may be electrically connected between the first redistribution pattern and the second redistribution pattern. Thus, the fan-out type semiconductor package may have an improved heat dissipation characteristic with a thin thickness.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myungsam Kang, Youngchan Ko, Yongjin Park
  • Patent number: 11387131
    Abstract: An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Kioxia Corporation
    Inventors: Miki Toshima, Osamu Yamane
  • Patent number: 11373925
    Abstract: A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 28, 2022
    Assignee: LIGHT-MED (USA), INC.
    Inventors: Yongjun Huo, Chin Chung Lee
  • Patent number: 11373907
    Abstract: A method of manufacturing a device chip includes applying, from a front surface of a wafer formed with devices in a plurality of regions partitioned by a plurality of crossing division lines, a laser beam of such a wavelength as to be absorbed in the wafer along the division lines, to form V-shaped laser processed grooves along the division lines, the laser processed grooves becoming shallower toward outer sides in a width direction; adhering an adhesive tape to the front surface of the wafer formed with the laser processed grooves; and grinding the wafer held by a chuck table, with the adhesive tape interposed therebetween, from a back surface, to divide the wafer while thinning the wafer to a finished thickness, thereby forming a plurality of device chips having inclined surfaces at outside surfaces thereof.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 28, 2022
    Assignee: DISCO CORPORATION
    Inventor: Satoshi Kumazawa
  • Patent number: 11374047
    Abstract: An image sensor including a substrate having a first, a first device isolation region adjacent to the first surface and defining a unit pixel, a transfer gate on the first surface at an edge of the unit pixel, a photoelectric conversion part in the substrate and adjacent to a first side surface of the transfer gate, and a floating diffusion region in the substrate and adjacent to a second side surface of the transfer gate. The second side surface faces the first side surface. The first device isolation region is spaced apart from the second side surface. The substrate and the first device isolation region are doped with impurities having a first conductivity. A first impurity concentration of the first device isolation region is greater than a second impurity concentration of the substrate.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 28, 2022
    Inventors: SeungSik Kim, Sungchul Kim, Haeyong Park
  • Patent number: 11373981
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Patent number: 11373968
    Abstract: A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 28, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Yaoyu Pang, Steven A. Atherton
  • Patent number: 11362054
    Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunsoo Chung, Taewon Yoo, Myungkee Chung
  • Patent number: 11362049
    Abstract: A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: June 14, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 11362067
    Abstract: A method of manufacturing a semiconductor device according to example embodiments includes: sequentially forming first through third insulating layers on a substrate; forming an opening by etching the first through third insulating layers; forming a conductive layer configured in the opening; forming a fourth insulating layer in the opening after the forming of the conductive layer; and removing a portion of an edge region of the substrate after the forming of the fourth insulating layer.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 14, 2022
    Inventors: Kyuha Lee, Pilkyu Kang, Seokho Kim, Hoonjoo Na, Kwangjin Moon, Jaehyung Park, Joohee Jang, Yikoan Hong
  • Patent number: 11362069
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a filling material is provided. The first die has a first bonding structure, and the first bonding structure includes first bonding pads and a first heat dissipating element. The second die has a second bonding structure, and the second bonding structure includes second bonding pads and a second heat dissipating element. The first bonding pads are bonded with the second bonding pads. The first heat dissipating element is connected to one first bonding pad of the first bonding pads and the second heat dissipating element is connected to one second bonding pad of the second bonding pads. The filling material is disposed over the first die and laterally around the second die. The first and second dies are bonded through the first and second bonding structures.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11362028
    Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: June 14, 2022
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Satoru Kuramochi, Sumio Koiwa, Hidenori Yoshioka
  • Patent number: 11355469
    Abstract: One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 7, 2022
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Tetsuyuki Shirakawa, Takahiro Fukui, Shinnosuke Iwamoto