Patents Examined by Wilner Jean Baptiste
  • Patent number: 10388619
    Abstract: A semiconductor device and a manufacturing method thereof, which can reduce a size of the semiconductor device. As a non-limiting example, various aspects of this disclosure provide for a reduction in package size based at least in part on patterning techniques for forming interconnection structures.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: August 20, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Woong Hong, Jun Park, Kyung Han Ryu
  • Patent number: 10381320
    Abstract: The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at %, and a balance being made up of Ag and incidental impurities.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: August 13, 2019
    Assignees: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD., NIPPON MICROMETAL CORPORATION
    Inventors: Tetsuya Oyamada, Tomohiro Uno, Hiroyuki Deai, Daizo Oda
  • Patent number: 10381323
    Abstract: Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10373927
    Abstract: A connection body includes a circuit board terminals arranged into terminal rows, the terminals rows being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the terminals are arranged, and an electronic component including bumps arranged into bump rows corresponding to the terminal rows, the bumps being arranged in parallel to one another in a widthwise direction orthogonal to a direction in which the bumps are arranged. The electronic component is connected upon the circuit board interposed by an anisotropic conductive adhesive including electrically conductive particles arranged therein. A distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward the outer sides of the circuit board and the electronic component is greater than a distance between mutually opposing terminals of the terminals and bumps of the bumps arranged toward their inner sides.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 6, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Reiji Tsukao
  • Patent number: 10374056
    Abstract: Disclosed is a method for producing a transistor device and a transistor device. The method includes: forming a source region of a first doping type in a body region of a second doping type in a semiconductor body; and forming a low-resistance region of the second doping type adjoining the source region in the body region. Forming the source region includes implanting dopant particles of the first doping type using an implantation mask via a first surface of the semiconductor body into the body region. Implanting the doping particles of the first doping type includes a tilted implantation.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Katarzyna Kowalik-Seidl, Bjoern Fischer, Winfried Kaindl, Markus Schmitt, Matthias Wegscheider
  • Patent number: 10355072
    Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zeng Wang, Wei Si, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 10347628
    Abstract: Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan V. V. S. Surisetty
  • Patent number: 10333097
    Abstract: An OLED display device includes an assisting conductive layer formed on a bottom surface of an upper substrate in such a way that the assisting conductive layer is in direct contact with and electrically connected to a second electrode that is located on a top surface of a lower substrate so that electrical conduction capability of the second electrode is enhanced and the electrical resistance of the second electrode is reduced to thereby make in-plane voltage homogenous, improve consistency of displaying, and alleviate the issues of non-uniform panel brightness and mura and also help reduce the thickness of the second electrode for saving material of the second electrode and increase light transparency of the second electrode.
    Type: Grant
    Filed: May 20, 2018
    Date of Patent: June 25, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wenhui Li, Wen Shi
  • Patent number: 10329143
    Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics (Malta) Ltd
    Inventor: Kevin Formosa
  • Patent number: 10326002
    Abstract: Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Ruilong Xie, Scott Beasor, Zhenyu Hu
  • Patent number: 10325834
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Patent number: 10297541
    Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Mooi Ling Chang, Eng Huat Goh, Say Thong Tony Tan, Tin Poay Chuah
  • Patent number: 10297782
    Abstract: An OLED display device includes an assisting conductive layer formed on a bottom surface of an upper substrate in such a way that the assisting conductive layer is in direct contact with and electrically connected to a second electrode that is located on a top surface of a lower substrate so that electrical conduction capability of the second electrode is enhanced and the electrical resistance of the second electrode is reduced to thereby make in-plane voltage homogenous, improve consistency of displaying, and alleviate the issues of non-uniform panel brightness and mura and also help reduce the thickness of the second electrode for saving material of the second electrode and increase light transparency of the second electrode.
    Type: Grant
    Filed: May 20, 2018
    Date of Patent: May 21, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wenhui Li, Wen Shi
  • Patent number: 10290561
    Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Edvin Cetegen, Omkar G. Karhade, Kedar Dhane, Chandra M. Jha
  • Patent number: 10283466
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 7, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10280107
    Abstract: The present invention relates to a method for separating solid-body slices (1) from a donor substrate (2). The method comprises the steps of: producing modifications (10) within the donor substrate (2) by means of laser beams (12), wherein a detachment region is predefined by the modifications (10), along which detachment region the solid-body layer (1) is separated from the donor substrate (2), and removing material from the donor substrate (2), starting from a surface (4) extending in the peripheral direction of the donor substrate (2), in the direction of the center (Z) of the donor substrate (2), in particular in order to produce a peripheral indentation (6).
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 7, 2019
    Assignee: Siltectra, Gmbh
    Inventors: Marko Swoboda, Christian Beyer, Franz Schilling, Jan Richter
  • Patent number: 10262915
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 16, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 10256176
    Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture 5 being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planar view is smallest among a plurality of areas of the through-hole in a planar view, a filler arranged within the 10 through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: April 9, 2019
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Satoru Kuramochi, Sumio Koiwa, Hidenori Yoshioka
  • Patent number: 10256248
    Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani, Hiroyuki Ogawa, Chun Ge, Daxin Mao, Yanli Zhang, Alexander Chu, Yan Li
  • Patent number: 10256174
    Abstract: A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction the first length being larger than the first width, and includes a plurality of through holes spaced apart from each other in the first direction; a semiconductor chip including a plurality of pads; and a plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Na-rae Shin, Jun-ho Song, Ji-yong Park, Kyoung-suk Yang, Hee-jung Hwang, Young-hun Jung