Patents Examined by Wilner Jean Baptiste
  • Patent number: 10892169
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a plurality of fourth transistors overlaying, at least in part the third transistors; a second metal layer overlaying, at least in part the fourth transistors; where the fourth transistors are aligned with less than 100 nm misalignment to the first transistors, where at least one of the plurality of vias has a radius of less than 200 nm, where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 12, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10892317
    Abstract: A method for forming a trench capacitor without an additional mask adder and the resulting device are provided. Embodiments include forming a buried implant layer over a substrate; forming an EPI layer over the buried implant layer; forming an oxide layer over the EPI layer; forming a nitride layer over the oxide layer; forming first and second trenches in the nitride layer, the oxide layer, the EPI layer, the buried implant layer and the substrate, the first trench being wider and deeper than the second trench; forming a dielectric layer in the trenches; forming a first polysilicon layer over the dielectric layer in the trenches; removing the first polysilicon layer and the dielectric layer above the EPI layer in the trenches and at a bottom of the first trench; and forming a second polysilicon layer filling the first trench and above the EPI layer in the second trench.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 12, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zeng Wang, Wei Si, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 10886238
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 10886399
    Abstract: A semiconductor device, such as a laterally diffused metal-oxide-semiconductor (LDMOS) transistor, includes a semiconductor substrate in which a source region and a drain region are disposed. The drain region has a drain finger terminating at a drain end. A gate structure is supported by the semiconductor substrate between the source region and the drain region, the gate structure extending laterally beyond the drain end. A drift region in the semiconductor substrate extends laterally from the drain region to at least the gate structure. The drift region is characterized by a first distance between a first sidewall of the drain finger and a second sidewall of the gate structure, and the gate structure is laterally tilted away from the drain region at the drain end of the drain finger to a second distance that is greater than the first distance.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 5, 2021
    Assignee: NXP USA, Inc.
    Inventor: Philippe Renaud
  • Patent number: 10872903
    Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 10872852
    Abstract: A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10867846
    Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate structure over a fin structure. The method also includes forming an S/D contact structure over a S/D structure and depositing a protection layer over the S/D contact structure. The protection layer and the S/D contact structure are made of different materials. The method further includes forming an etching stop layer over the protection layer and forming a dielectric layer over the etching stop layer. The method includes forming a first recess through the dielectric layer and the etching stop layer to expose the protection layer and forming an S/D conductive plug in the first recess. The S/D conductive plug includes a barrier layer directly on the protection layer, and the protection layer and the barrier layer are made of different materials.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Yuan Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 10861707
    Abstract: A method for manufacturing a semiconductor device includes forming a sacrificial member on a foundation layer, the sacrificial member extending in a first direction along a front surface of the foundation layer; forming a line and space pattern including a plurality of structures on the foundation layer and the sacrificial member, the structures extending along the front surface of the foundation layer in a second direction crossing the first direction; and forming communication passages between the foundation layer and the structures by selectively removing the sacrificial member via spaces between the structures, the spaces being in communication with each other through the communication passages.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Furukawa
  • Patent number: 10862070
    Abstract: There is provided a display device and an electronic apparatus that suppress leakage of a drive current between adjacent light emitting elements. A display device includes a plurality of light emitting elements having an organic light emitting layer sandwiched between a first electrode disposed for each of the light emitting elements and a second electrode in a lamination direction and arrayed on a plane, and an insulating layer disposed between the first electrodes. At least a part of a film thickness region in the insulating layer contains a positively charged inorganic nitride.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 8, 2020
    Assignee: SONY CORPORATION
    Inventor: Kazuichiro Itonaga
  • Patent number: 10847446
    Abstract: A construction of integrated circuitry comprises a trench isolation region in semiconductive material. The trench isolation region comprises laterally-opposing laterally-outermost first regions which comprise a first material and a second region laterally-inward of the first regions. The second region comprises a second material of different composition from that of the first material. A diffusion region is in the uppermost portion of the semiconductive material directly against a sidewall of one of the first regions. Insulator material is above the trench isolation region and the diffusion region. An elevationally-elongated conductive via is in the insulator material and extends to the diffusion region and the trench isolation region. The conductive via laterally overlaps the diffusion region and the one first region.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yuko Togashi
  • Patent number: 10847414
    Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10847493
    Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing, Ltd.
    Inventors: Chen-Hua Yu, Chen-Shien Chen
  • Patent number: 10847447
    Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Lyong Kim, Seungduk Baek
  • Patent number: 10847676
    Abstract: Disclosed in one embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; a second electrode electrically connected with the second conductive semiconductor layer; a reflective layer arranged on the second electrode; and a capping layer arranged on the reflective layer and including a plurality of layers, wherein the capping layer includes a first layer directly arranged on the reflective layer and the first layer includes Ti.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 24, 2020
    Assignee: LG Innotek Co., Ltd.
    Inventors: Youn Joon Sung, Ki Man Kang, Min Sung Kim, Su lk Park, Yong Gyeong Lee, Eun Dk Lee, Hyun Soo Lim
  • Patent number: 10840240
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10832978
    Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 10, 2020
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Patent number: 10825792
    Abstract: Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10825771
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, a first element disposed at least in a lower layer portion of the insulating film, a second element disposed at least in the lower layer portion of the insulating film, and a hydrogen barrier member provided on the semiconductor substrate. The hydrogen barrier member is made from a material transmitting hydrogen less easily than does a material of the insulating film. The hydrogen barrier member and the semiconductor substrate surround the second element. The hydrogen barrier member does not surround the first element.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 3, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Nobuyuki Toda, Takeshi Yamamoto, Shinji Kawahara, Kazuaki Yamaura, Takashi Ishikawa
  • Patent number: 10825764
    Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
  • Patent number: 10825786
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney