Abstract: A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.

Abstract: A computer system having a primary serial bus and one or more serial sub-busses separated from the primary serial bus by gating devices is described. By selectively enabling different gating devices (thereby coupling one serial sub-bus to the primary serial bus at a time), each sub-bus may support the maximum number of addressable devices. This, in turn, expands the effective serial bus address space of the computer system.

Abstract: A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than the others and including a peripheral device. Each master may request control of the shared bus and is adapted to perform short transfers and long burst transfers on the shared bus between a resource and the master. A shared bus arbiter is utilized for dynamically determining the highest priority request between a number of shared bus requests, and granting control of the shared bus to the highest priority requesting bus master.

Abstract: A device for extending functions of a computer connected thereto adds a new function to functions of an existing extension unit. The device includes a non-volatile memory and a new extension unit connected to the non-volatile memory and capable of being connected to the computer via a bus and to the existing extension unit. The new extension unit transfers what is stored in the non-volatile memory to the computer when the computer requests attribute information of the existing extension unit.

Abstract: A portable computer system with universal serial bus (USB) port or ports and a method for controlling power of the universal serial bus (USB) port is described. When the main power of the portable computer system is supplied from a battery rather than an alternating current (AC) adapter, the power of the universal serial bus (USB) port is automatically shut down. In addition, the power of the universal serial bus (USB ) port is completely shut down while the universal serial bus (USB) port is not used in response to a setting state of the universal serial bus (USB) port, thereby reducing unnecessary power consumption. Further, when an over-current is detected from the alternating current (AC) adapter or the battery, the power of the universal serial bus (USB) port is shut down, whereby damage to peripheral devices coupled to the universal serial bus (USB) port can be prevented.

Abstract: A method, system and computer program product are provided for detecting the presence of devices, particularly hot plug devices, connected to a bus both during start-up of a computer system and while the system is running. At start-up, and periodically thereafter, all possible device connections are polled by microprocessors, called sub-bus controllers, which include logic for generating a map of components present on each bus. Each map is accessible by the master bus controller. During system run-time, periodic polling, may be continuous thereby providing a real time device status map for every available bus connection.

Abstract: A system includes a bus and devices capable of supporting multiple data transfer rates coupled to the bus. Each device includes a storage element storing a value indicating the supported transfer rates. A routine is adapted to update the value in the storage element of at least one device to indicate that one or more data transfer rates are unsupported by the device. The bus may include an Accelerated Graphics Port (AGP) bus.

Abstract: A communication link is used both as a primary communication link and as a subordinate link in a computer system. A first integrated circuit having a plurality of first functions and a second integrated circuit having a plurality of second functions, are connected via a first communication link. The first communication link includes a plurality of first logical pipes carrying transactions on the first communication link, each of the first logical pipes having a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. A second communication link is coupled to the first communication link and includes a plurality of second logical pipes carrying transactions on the second communication link, each of the second logical pipes has a source end and a target end. A target (or source) end of one of the first pipes is communicatively coupled on the second integrated circuit to a source (or target) end one of the second pipes.

Abstract: A method and system for monitoring and adapting to configuration changes in a data processing system having a known configuration, while power is applied thereto. In response to a configuration change in the data processing system, values are calculated for multiple system operating factors. An alert is provided to a user if at least one of said calculated values, among the multiple system operating factors, is not within a predetermined range of values for the multiple system operating factors. In addition, the operation of the data processing system is restricted to accommodate for any system operating factors which are not within the predetermined range of values, such that the data processing system is guarded from damage due to an unstable configuration.

Abstract: A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.

Abstract: A computer monitor includes a plurality of screen-control switches, an input/output circuit adapted to be connected to a computer, and a processor connected to the screen-control switches and the input/output circuit, and adapted to detect if a universal serial bus (USB) standard compliant-interface was established between the input/output circuit and the computer. The processor performs a hardware-based on-screen display routine to adjust screen characteristics of the computer monitor when the screen-control switches are operated and the USB standard compliant-interface is not detected. The processor generates a command that is assigned to an operated one of the screen-control switches and that is to be received by the computer via the USB standard compliant-interface when the USB standard compliant-interface is detected.

Abstract: A digital signal processing apparatus for processing a plurality of video signals and a plurality of audio signals is provided, and comprises a computer comprising a system bus and a main CPU connected to the system bus and an extension processor comprising a plurality of signal processing circuits for processing the plurality of video signals and/or the plurality of audio signals, and a local CPU for controlling the plurality of signal processing circuits so as to allow for the processing of the video signals and audio signals in real time. The extension processor further comprises an extension system bus extended from the system bus, a digital audio video (DAV) bus for transmitting the plurality of video signals and the plurality of audio signals between the plurality of signal processing circuits and a local CPU bus for transmitting control signals outputted from the local CPU.

Abstract: In a computer system including one or more hosts coupled via a host bus to each other and a cached host memory, an Input/Output processor providing data to peripheral devices and an I/O bus disposed between the hosts and the Input/Output processor for transfer of information therebetween, an inbound queue structure receives message information from one of the hosts, and an outbound queue structure sends message information from the I/O processor to one of the hosts. Each of the queue structures comprises a pair designated as a free-list buffer and a post-list buffer. The free-list buffer of the inbound queue structure and the post-list buffer of the outbound queue structure are locally coupled to the hosts so that message information transfers between these two buffers and the hosts without incurring I/O bus read operations.

Abstract: A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

Abstract: A hot dockable computer system comprises an enhanced expansion bus bridge for coupling the computer system to a docking station. The enhanced bus bridge includes an ACPI control unit for controlling the power state of the bridge device and associated buses. The ACPI control unit receives a docking signal from a docking connector on the computer that is asserted to indicate when a docking sequence has completed. When the docking signal is asserted, the bus bridge transmits a PME interrupt to the operating system, which activates the bus bridge. The bus bridge further includes a plurality of switches coupling the expansion bus signals in the computer system to the expansion bus signals in the dock. The ACPI control unit opens the switches when the bus bridge is deactivated, decoupling the expansion bus in the computer from the expansion bus in the dock. Similarly, the ACPI control unit deasserts the control signal to close the switches when the bus bridge is activated, connecting the expansion buses.

Abstract: There is provided an automatic transaction apparatus having a receiver for receiving a plurality of types of transaction media (e.g. application form, identification) in accordance with transaction procedures from a user. When power failure is occurred while the transaction medium is in the receiver, and in case that the medium in the receiver is one that does not have to be returned to the user (e.g. application form), the receiver does not return the medium, in case that the medium in the receiver is one that have to be returned to the user (e.g. identification), the receiver provides opportunity for the user to get back the medium.

Abstract: Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Abstract: A method and circuit for performing a wired-or function in a differential transmission environment are disclosed. The wired-or function is realized by enabling the differential driver portion of the differential transceiver when the signaling path is to be driven with a logical true signal and disabling the differential driver portion when a logical false signal is to transmitted to the signaling path. In a preferred embodiment, a 1394 backplane node (a node is a single connection to the bus which may or may not be shared by multiple devices) is implemented using commercially available chips including a physical arbiter, a link controller, a differential transceiver, a programmable logic device, and some additional transistors.

Abstract: An embodiment of the invention is directed at a method of processing multiple delayed write transactions, such as PCI transactions, by a bridge. The method involves receiving a number of requests for delayed write transactions on an initiating side of the bridge, and storing received transaction information for each of the requests in a separate one of a number of storage elements. An element containing newly received transaction information is marked valid if no received transaction information in other elements matches the newly received transaction information. Then, a delayed write transaction corresponding to the valid element is mastered on a target side of the bridge. If the corresponding delayed write transaction is completed on the target side, then the valid element is marked as complete. Thereafter, a new request received on the initiating side is signaled a successful termination if received transaction information for the new request matches that stored in the valid and complete element.