Abstract: A plug has a plug casing, an inner tube received in the plug casing and having two recesses oppositely defined in a top of the inner tube to receive therein a first blade and a second blade, a fuse tube having therein a spring, a fuse retainer with legs extending out therefrom and a fuse. The spring abuts the fuse retainer and the legs securely clamp the fuse. A fuse engaging ring is connected to the fuse tube. A connecting ring is engaged with the inner tube to electrically connect to the first connecting leg of the fuse engaging ring. After the connection of the connecting ring to the inner tube which has the fuse tube, the spring, the fuse retainer and the fuse therein, the fuse electrically connects to the fuse engaging ring and therefore the connecting ring.

Abstract: A method for suspending and resuming a computer system without being affected by an abnormal power failure. The relevant operating information and context of the related devices are stored in both a memory and a hard disk before the computer system enters into a sleep state. If a power failure occurs, relevant operating information of the system can still be fetched from the hard disk to restore the computer system to its original operating state even though the information saved in the memory is lost. Also, the computer system can self turn on and activate a “wake on LAN” function and a “ring in wake up” function when power resumes after a sudden power failure before entering into the soft-off state. Therefore, users and system administrator can wake up the computer system from a remote site in a very convenient way.

Abstract: The present invention provides a PCI bus switching architecture to allow a pair of PCI processors to have access to a common set of PCI I/O cards. More specifically, this design allows either cross-coupled processor to dynamically take over the operational controls of the common set of PCI I/O cards if the primary processor for the same become inoperative. The present invention achieves the objective by employing a point to point data link connection between each processor and their respective controllers for each common set of PCI I/O cards associated with a PCI bus.

Abstract: A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plurality of pipes carrying transactions on the link. Each pipe has a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. Each of the pipes is identified by a pipe identifier that uniquely identifies both the source end and the target end of a respective pipe. Each transaction on the link includes a pipe identification field containing the pipe identifier to associate each of the transactions with one of the pipes. The pipes share the link on a packet multiplexed basis. Each pipe can carry either isochronous or asynchronous transactions.

Abstract: An apparatus and method for controlling the number of interrupts a data transfer unit generates to a CPU is disclosed. A pacing unit is used to register attempted data transfers (events) from a data transfer unit to a CPU and compares this value to a user defined threshold limit. When the number of events reaches the threshold limit, an interrupt is generated to the CPU.

Abstract: In this invention, the bus of a computer body is connected to the bus of an expansion unit through a serial interface so as to implement connection wirings in the form of a serial cable. A PCI-PCI bridge for connecting a primary PCI bus to a secondary PCI bus comprises two physically isolated controllers, i.e., a primary PCI serial transfer controller implemented on the PC body side and a secondary PCI serial transfer controller implemented on the docking station side. The two controllers are connected to each other through serial LVDS lines. Transactions are exchanged between the primary PCI bus and the secondary PCI bus by serial transfer between the primary PCI serial transfer controller and the secondary PCI serial transfer controller.

Abstract: In this invention, serial transmission suitable for signal lines in which a transformer is inserted is realized by using existing differential buffers. Differential output buffers are connected in parallel with each other. A differential signal line pair in which a transformer is inserted is driven by these two differential output buffers. In this case, a voltage between the two lines of the differential signal line pair is determined by a combination of outputs from the two differential output buffers, and three values, i.e., “+V”, “−V”, and “zero”, can be output. By using this ternary data, serial signal transmission based on the bipolar transfer mode can be performed, and serial transmission suitable for the signal lines in which the transformer is inserted can be realized.

Abstract: A method for controlling power of a computer system using a wake up local area network (LAN) signal and an apparatus therefor are provided. The method includes the steps of powering devices other than predetermined peripheral apparatuses sensible to power on/off, when the wake up LAN signal is sensed in the power-off state of the computer system, checking power on enable or disable in wake up LAN enable from the system setup state during booting of the computer, and powering on the predetermined peripheral apparatuses if a system is set to power on enable, and powering off the devices powered on in the step of checking power on enable or disable if not.

Abstract: A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged.

Abstract: Sets of future risk expectation strings for long term care and for life expectancy are categorized into a plurality of Joint Equal Age Risk Classifications, upon which risk exposure sequencing and present risk value analysis are applied to calculate joint equal age present risk values that are inputted into a Joint Equal Age Risk Chart; future risk expectation strings for long term care and for life expectancy are also categorized into a plurality of Age Differential Classifications, which are distinct and independent from the separately categorized Joint Equal Age Classifications. Risk exposure sequencing and present risk value analysis are applied to calculate temporary joint equal age present risk values and temporary differential present risk values, which are compared to generate temporary age equivalence differentials that are inputted into a temporary age equivalence matrix from which an age differential adjustment factors are drawn and inputted into an Age Differential Adjustment Chart.

Abstract: A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.

Abstract: An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit.

Abstract: A system for extending in length a connection from a universal serial bus (USB) peripheral device to a computer beyond the length enabled by the device hardware.

Abstract: A method and apparatus is described that is related to repeating (extending) transactions on a bus. A plurality of buffer pairs are configured to direct a plurality of signals between a first bus and a second bus in a bus cycle. A circuit is configured to monitor a control signal to determine a bus location of a master device and the circuit is further configured to enable one buffer in the buffer pairs to control a direction of the plurality of signals between the first bus and the second bus.

Abstract: A computer system (10) includes a plurality of hot-plug sockets (30-33), each of which can be selectively uncoupled from a bus (59) during normal system operation, in order to facilitate insertion or removal of module (36). A clock signal (PCLK) is generated at one of two different frequencies, and at system power-up a clock arbitration circuit (47) is responsive to modules which are present for specifying a speed of the clock signal. A hot-plug controller circuit (18) can selectively uncouple one of the hot-plug sockets from the bus during normal operation to facilitate insertion or removal of a module, and also facilitates a determination of whether clock speed requirements of an inserted module are compatible with the current clock speed. The selected socket is recoupled to the bus only if the inserted module is compatible with the current clock speed.

Abstract: An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code.

Abstract: A system is described in which the Master can stop its clock and go into a low-power state (for power conservation reasons) at arbitrary times. Before going into the stopped-clock or low-power mode, the Master checks that the serial bus is idle (defined as both Clock and Data lines being “High”). A latch circuit is provided which is active when them aster is in low-power mode. The latch circuit watches for the very first negative-going clock pulse (from the slave), and its configuration is such that when latched, it holds the clock line low. Holding the clock line low prompts the slave to discontinue efforts to send the data. Stated differently, the slave will not conclude that it had successfully sent its data, and this prompts the slave to retain a copy of its data for later resending.

Abstract: A power supply unit for a computer system is proposed which has at least one data memory unit, which provides data specific to the power supply unit, for system controllers in the computer system. This achieves the object of offering the capability of ensuring that the power supply unit is not overloaded or underloaded, or that an appropriate message is output to the outside world, without having to explicitly know all the possible operational situations even in the development phase of the power supply unit.

Abstract: A system includes a bus and devices capable of supporting multiple data transfer rates coupled to the bus. Each device includes a storage element storing a value indicating the supported transfer rates. A routine is adapted to update the value in the storage element of at least one device to indicate that one or more data transfer rates are unsupported by the device. The bus may include an Accelerated Graphics Port (AGP) bus.

Abstract: An information processing device includes an OS having an interrupt processing function and an OS support system which is activated through initialization of the OS. The OS support system includes an interrupt managing section for recording the contents of an interrupt process requiring a high realtime performance, and an interrupt judging section for receiving an interrupt request earlier than the OS does when the interrupt request occurs in the information processing device, and judging whether the interrupt request corresponds to the interrupt process recorded in the interrupt managing section. The OS support system further includes an interrupt executing section for executing the recorded interrupt process when the interrupt request corresponds to the recorded interrupt process. The OS support system causes the OS to execute an interrupt process which is not recorded in the interrupt managing section.