Patents Examined by Xia L Cross
  • Patent number: 11031344
    Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 11024759
    Abstract: Provided is an electronic device containing: a two-dimensional semiconductor material; and another heterogeneous material adjacent to the two-dimensional semiconductor material, wherein the heterogeneous material is doped with an impurity of a type different from the two-dimensional semiconductor material or has a band gap different from the two-dimensional semiconductor material.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 1, 2021
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sung-Yool Choi, Gwang Hyuk Shin
  • Patent number: 11024724
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11011624
    Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Michael P. Belyansky, Choonghyun Lee
  • Patent number: 11004986
    Abstract: It is an object of the present invention to provide a technique of preventing electric-field concentration in a first P-type semiconductor layer during recovery operation. A semiconductor device includes a drift layer, an N-type semiconductor layer, a first P-type semiconductor layer, a second P-type semiconductor layer, an electrode, and an insulating layer. The N-type semiconductor layer and the first P-type semiconductor layer are disposed below the drift layer while being adjacent to each other in a lateral direction. The insulating layer is disposed above the first P-type semiconductor layer while being in contact with the second P-type semiconductor layer and the electrode.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: May 11, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Akito Nishii
  • Patent number: 10991814
    Abstract: Disclosed are a three-dimensional tunneling field-effect transistor and a method of fabricating the same. A method of fabricating a three-dimensional tunneling field-effect transistor according to an embodiment of the present disclosure includes growing a buffer layer, an embedded source layer, an etch stop layer, an active source layer, a channel layer, and a drain layer on a substrate; depositing a metal layer on the drain layer, and then forming a pattern in a mesa structure shape; forming a vertical gate at one end of each of the etch stop layer, the active source layer, the channel layer, and the drain layer; isolating the active source layer from the substrate to form a first air bridge; isolating the drain layer from the substrate to form a second air bridge; and isolating the vertical gate from the substrate to form a third air bridge.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Chang Hwan Choi, Dong Hwan Lim
  • Patent number: 10985106
    Abstract: A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Ha Gyeong Song
  • Patent number: 10978554
    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang
  • Patent number: 10950593
    Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 16, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Patent number: 10944070
    Abstract: A display device having improved reliability includes: a display panel including a substrate and an encapsulation layer, the substrate including a display area and a non-display area, and the encapsulation layer being located on the substrate at the display area; and a window on the display panel, and the substrate has a convex shape and has a plurality of first grooves arranged at an outer circumferential surface of the substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: March 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongho Kim, Youngjin Ko, Minsoo Kim
  • Patent number: 10937825
    Abstract: A method of producing an optoelectronic device includes providing an optical element including an optical lens and including a frame, wherein the frame projects with a receptacle section beyond a first side of the lens, the receptacle section of the frame surrounds a receptacle space, and the receptacle section of the frame includes a bearing face at an inner side; inserting an optoelectronic component and a transparent intermediate element into the receptacle space; placing the intermediate element onto the bearing face; and securing the component and the intermediate element to the frame.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 2, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Markus Burger, Markus Pindl, Markus Boss
  • Patent number: 10923594
    Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Dirk Utess, Peter Philipp Steinmann, Stephanie Wilhelm
  • Patent number: 10896894
    Abstract: Methods of fabricating semiconductor device packages may involve forming trenches in a first wafer. A dielectric material may be placed over a first active surface. Electrically conductive elements may be operatively connected to bond pads of a second wafer with the dielectric material interposed between the first wafer and the second wafer. Force may be applied to the first wafer and the second wafer while exposing the first wafer and the second wafer to an elevated temperature. Portions of the dielectric material may flow into the trenches. The elevated temperature may be reduced to at least partially solidify the dielectric material. A thickness of the first wafer may be reduced to reveal the portions of the dielectric material in the trenches. The first wager may be singulated and the second wafer may be singulated to form semiconductor dice.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Wei Zhou
  • Patent number: 10879340
    Abstract: A tiling display device includes a plurality of display modules arranged on one plane. The display module includes a substrate, a signal line, an open hole, a filling layer, and a circuit board. The substrate has a display area in which subpixels are defined. The signal line is positioned on the top surface of the substrate within the display area to deliver a predetermined signal to the subpixels. The open hole is provided to penetrate the substrate within the display area. The filling layer fills the open hole. The circuit board is positioned on the back surface of the substrate and electrically connected to the signal line through the filling layer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 29, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Seungjae Lee, Jungwoo Ha, Yoowhan Kim
  • Patent number: 10804288
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Arai
  • Patent number: 10790410
    Abstract: An optoelectronic device configured for improved light extraction through a region of the device other than the substrate is described. A group III nitride semiconductor layer of a first polarity is located on the substrate and an active region can be located on the group III nitride semiconductor layer. A group III nitride semiconductor layer of a second polarity, different from the first polarity, can located adjacent to the active region. A first contact can directly contact the group III nitride semiconductor layer of the first polarity and a second contact can directly contact the group III nitride semiconductor layer of the second polarity. Each of the first and second contacts can include a plurality of openings extending entirely there through and the first and second contacts can form a photonic crystal structure. Some or all of the group III nitride semiconductor layers can be located in nanostructures.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: September 29, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Grigory Simin, Alexander Dobrinsky
  • Patent number: 10790352
    Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiefeng Lin, Hsiao-Lan Yang, Chih-Yung Lin
  • Patent number: 10777663
    Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 15, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Fang-Liang Lu, Pin-Shiang Chen, Chee-Wee Liu
  • Patent number: 10770540
    Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Andrew Vladimir Claude Cervin, Marina Zelner
  • Patent number: 10748973
    Abstract: A display device includes a display panel including a lower surface, an upper surface facing the lower surface, and a first area, a first film positioned below the lower surface and provided with a film groove defined therein overlapping with the first area, a second film disposed on the upper surface, and an adhesive layer disposed between the lower surface of the display panel and the first film and provided with an adhesive groove defined therein overlapping with the first area. The first area extends across the display panel along a first direction, one side surface of the adhesive groove is defined by one line when viewed in a cross section taken along a second direction crossing the first direction, and one side surface of the film groove is defined by two or more lines when viewed in the cross section taken along the second direction.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junghoon Han, Jihoon Kim, Daeseung Mun