Abstract: Disclosed are an organic light emitting display device and a method of manufacturing the same. In the organic light emitting display, an anode connected to a thin film transistor and a bank disposed along the edge of the anode are simultaneously formed through one mask process, and a partition is formed to cover the side surface of the anode, thereby preventing damage to a pad cover electrode by an etching solution or etching gas of the anode without any separate pad protective film.

Abstract: The present disclosure relates to a resistive random access memory device and a preparing method thereof.

Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and a flexible substrate region (30d) of a plastic film (30) of a multilayer stack (100) are divided, the interface between the plastic film (30) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into the first portion (110) and the second portion (120) while the multilayer stack (100) is kept in contact with the stage (212). The first portion (110) includes the intermediate region (30i) and a light-emitting device (1000) which are adhered to the stage (212). The light-emitting device (1000) includes a functional layer region (20) and the flexible substrate region (30d). The second portion (120) includes the glass base (10). The intermediate region (30i) adhered to the stage (212) is removed from the stage while the light-emitting device (1000) is kept adhered to the stage.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

Abstract: There is provided a method of manufacturing a display unit. The method includes forming a plurality of first electrodes, forming a functional layer that covers from the first electrode to an inter-electrode region, and locally applying an energy ray to the functional layer to form a disconnecting section or a high-resistance section in the functional layer in the inter-electrode region.

Abstract: A method of manufacturing a light emitting device includes: bonding a plurality of light emitting elements each having an outer peripheral lateral surface onto a light-transmissive substrate; forming at least one groove on the light-transmissive substrate to surround an outer periphery of each of the plurality of light emitting elements; disposing at least one light guiding member in the groove to continuously cover the groove and the outer peripheral lateral surfaces of adjacent ones of the plurality of light emitting elements; and singulating the light-transmissive substrate at a position between adjacent ones of the plurality of light emitting elements, to obtain a plurality of light emitting devices in each of which at least one of the light emitting elements is bonded to a single light-transmissive member.

Abstract: An organic electroluminescent display panel is provided, comprising a planarization layer; a pixel electrode formed on the planarization layer; and an auxiliary electrode coated by the planarization layer. The planarization layer defines a contact hole extending to a top surface of the planarization layer to have the auxiliary electrode contacted with the corresponding pixel electrode. A display device comprising the organic electroluminescent display panel and a method for manufacturing the organic electroluminescent display panel are further provided.

Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: A display unit including a first substrate and a second substrate that are disposed to face each other, a first organic insulating layer on the first substrate, a plurality of light-emitting elements arrayed in a display region, the display region on the first organic insulating layer and facing the second substrate and a first moisture-proof film covering the first organic insulating layer in a peripheral region, in which the peripheral region is provided on the first substrate and surrounds the display region.

Abstract: A semiconductor memory device includes a first conductive layer, second conductive layers extending in a first direction and stacked above the first conductive layer in a second direction, a third conductive layer between the first conductive layer and the second conductive layers, a memory pillar extending inside the second conductive layers in the second direction, a first insulating layer that isolates the second conductive layers in a third direction, and second insulating layers spaced from an end of the first insulating layer and extending in the third direction. The second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction. The first conductive layer includes a region that overlaps in the second direction a region where extension lines of the first and second insulating layers intersect, and the third conductive layer does not overlap this intersection region in the second direction.

Abstract: A display device includes a display substrate including at least one step portion, and a thin film encapsulation layer above the display substrate, the thin film encapsulation layer including a buffer layer configured to reduce a height difference due to the at least one step portion and a barrier layer above the buffer layer, the buffer layer including a plurality of sub-layers and interfaces between the plurality of sub-layers, and the interfaces including a curved surface changing from a concave shape to a convex shape toward a portion overlapping the step portion from an outer portion of the step portion.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor wafer, a plurality of semiconductor chips, and a plurality of first protection dams. The semiconductor wafer has a plurality of functional regions separated by a plurality of vertical streets and a plurality of horizontal streets. The semiconductor chips are mounted on the functional regions, respectively. The first protection dams are disposed on the vertical streets and the horizontal streets and spaced from the semiconductor chips. A height of the first protection dam is not less than a height of the semiconductor chip.

Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.

Abstract: The present invention relates generally to a pressing-type semiconductor power device package, and more specifically to a pressing-type semiconductor power device package in which a semiconductor chip, such as a transistor or diode, is formed into a package via a pressing structure without using any conductive adhesive, such as solder, which is used in the past, thereby improving production efficiency and durability.

Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.

Abstract: Provided is an electronic device containing: a two-dimensional semiconductor material; and another heterogeneous material adjacent to the two-dimensional semiconductor material, wherein the heterogeneous material is doped with an impurity of a type different from the two-dimensional semiconductor material or has a band gap different from the two-dimensional semiconductor material.

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

Abstract: It is an object of the present invention to provide a technique of preventing electric-field concentration in a first P-type semiconductor layer during recovery operation. A semiconductor device includes a drift layer, an N-type semiconductor layer, a first P-type semiconductor layer, a second P-type semiconductor layer, an electrode, and an insulating layer. The N-type semiconductor layer and the first P-type semiconductor layer are disposed below the drift layer while being adjacent to each other in a lateral direction. The insulating layer is disposed above the first P-type semiconductor layer while being in contact with the second P-type semiconductor layer and the electrode.

Abstract: Disclosed are a three-dimensional tunneling field-effect transistor and a method of fabricating the same. A method of fabricating a three-dimensional tunneling field-effect transistor according to an embodiment of the present disclosure includes growing a buffer layer, an embedded source layer, an etch stop layer, an active source layer, a channel layer, and a drain layer on a substrate; depositing a metal layer on the drain layer, and then forming a pattern in a mesa structure shape; forming a vertical gate at one end of each of the etch stop layer, the active source layer, the channel layer, and the drain layer; isolating the active source layer from the substrate to form a first air bridge; isolating the drain layer from the substrate to form a second air bridge; and isolating the vertical gate from the substrate to form a third air bridge.