Patents Examined by Xuxing Chen
  • Patent number: 12681658
    Abstract: Devices, systems, and methods for reconfigurable and/or updatable lightweight electronic devices or systems are disclosed. Via use of such a device, system, or method, various capabilities for a user are provided, simplified, secured, and/or made more convenient. The system may interact with various other devices or systems, including those that are cloud-based or communicate through the cloud, and may utilize various local sensors, in order to provide one or more of improved access, monitoring, user diagnostics, and so forth.
    Type: Grant
    Filed: March 19, 2025
    Date of Patent: July 14, 2026
    Assignee: Life365, Inc.
    Inventors: Kent Dicks, Eric Vandewater, Randolph Strength
  • Patent number: 12681558
    Abstract: A wireless device includes: a first circuit configured to perform normal operation of the wireless device in a normal operation mode and configured to be powered down in a power-down standby (PDS) mode; a second circuit at least including a low-power processor, a built-in battery, and an event detector, and configured to perform a power management function; a power source; and a switch configured between the first circuit and the power source and controlled by the second circuit to connect the first circuit to the power source or disconnect the first circuit from the power source. The power management function includes: in response to detecting a wake-up event by the event detector, changing the first circuit from the PDS mode to the normal operation mode; and in response to detecting a PDS event by the event detector, changing the first circuit from the normal operation mode to the PDS mode.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: July 14, 2026
    Assignee: MICRON ELECTRONICS LLC
    Inventor: Jun Xu
  • Patent number: 12683425
    Abstract: A method is provided, including: (a) providing an initial charging current to a battery; (b) receiving state information about the battery, including: (1) a temperature, (2) a load profile, and (3) a power loss temporal profile including power loss durations and timings of power failure events; (c) determining, based on the state information, a modification, including: (1) in response to detecting that (i) the temperature exceeds a first upper threshold or (ii) the load profile exceeds a second upper threshold, setting the modification to be a decrease in the charging current; and (2) in response to (iii) detecting that the load profile is below a lower threshold or (iv) predicting that the battery won't reach a full charge by a next expected power failure event if the initial charging current is maintained, setting the modification to be an increase in the charging current; and (d) in response to determining the modification, adjusting the charging current provided to the battery based on the determined modi
    Type: Grant
    Filed: August 27, 2024
    Date of Patent: July 14, 2026
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventors: Murali Krishna Kalvakunta, Sumandra Ghosh Chowdhury, Pradeep Tolakanahalli Nagabhushanrao
  • Patent number: 12675576
    Abstract: Methods, apparatus, and processor-readable storage media for secure boot and operating system management are provided herein. An example method includes configuring a first set of settings associated with a boot process for validating software components, where at least one of the software components is executed in a user space of an operating system. The method includes verifying, in response to obtaining a request to initiate the boot process, a second set of settings that is currently assigned to the boot process based on a comparison of the first set of settings and the second set of settings, and performing the boot process based on a result of the verifying, wherein the boot process comprises validating the software components based at least in part on the verified second set of settings and respective signatures computed for the software components, and initiating an automated action based on a result of the validating.
    Type: Grant
    Filed: April 24, 2024
    Date of Patent: July 7, 2026
    Assignee: Dell Products L.P.
    Inventors: Xinghai Yu, Colin Zou, Jin Wan
  • Patent number: 12663850
    Abstract: Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: June 23, 2026
    Assignee: Intel Corporation
    Inventors: Vikram B. Suresh, Sanu K. Mathew, Christopher Schaef, Chandra S. Katta, Long Sheng, Chin S. Park, Srinivasan Rajagopalan, Raju Rakha
  • Patent number: 12665766
    Abstract: The present disclosure relates to a method, a device, and a computer program product. The method includes: in response to receiving a calling command from a client, determining whether the calling command includes a security identifier. The method further includes, in response to determining that the calling command includes a security identifier, determining a security service corresponding to the security identifier in a firmware trusted platform module (FTPM). The method further includes performing security isolation and encryption processing on data related to the calling command by using the security service in the FTPM. In this way, the real intention of the calling command is concealed by the security identifier, which can reduce the possibility of attackers attacking or tampering with the calling command. Therefore, embodiments of the present disclosure enhance the security of the system, protect the device from potential attacks and damage, and prevent unauthorized accesses and malicious operations.
    Type: Grant
    Filed: May 31, 2024
    Date of Patent: June 23, 2026
    Assignee: Dell Products L.P.
    Inventors: Wenqing Peng, Jinpeng Liu, Tianxiang Chen, Bin He
  • Patent number: 12663828
    Abstract: There is provided an apparatus comprising first processing circuitry operating in a first clock domain having a first clock signal operating at a first clock period. The apparatus is provided with timeout period generation circuitry to couple with a second clock domain to generate a timeout clock signal, the second clock domain comprising second processing circuitry and having a second clock signal operating at a second clock period. The apparatus is provided with control circuitry to compare first data generated by the first processing circuitry against second data received from the second processing circuitry. The control circuitry is configured to indicate when the first and second data do not match within a timeout period. The timeout period generation circuitry is configured to receive second clock information indicative of the second clock period and to generate the timeout clock signal based on the second clock information and the first clock period.
    Type: Grant
    Filed: August 1, 2024
    Date of Patent: June 23, 2026
    Assignee: Arm Limited
    Inventors: Rohan Gaddh, Thomas Sean Houlihane
  • Patent number: 12656845
    Abstract: A PMIC includes a controller configured to determine, based on a configuration stored in the memory, a power on mode, when the power on mode indicates a dynamic power on operation, execute the dynamic power on operation by: determining, of the plurality of channels, a first channel associated with a first dynamic sequence number that is a lowest dynamic sequence number of the plurality of dynamic sequence numbers, enabling the first channel, monitoring the first channel to determine whether the first channel is in a first regulated state, and while monitoring the first channel, determining, of the plurality of channels, a second channel associated with a second dynamic sequence number of the plurality of dynamic sequence numbers, when the power on mode indicates a time based power on operation: iterating a slot counter through the plurality of slot numbers.
    Type: Grant
    Filed: August 16, 2024
    Date of Patent: June 16, 2026
    Assignee: NXP USA, Inc.
    Inventors: Daniel James Freeman, Joaquin Alberto Romo Torres, Michael Erik Lundahl
  • Patent number: 12645275
    Abstract: Methods, systems, and devices for using a backup capacitor as an alternate energy source via dynamic APL budgeting are described. A memory system may use excess power available at an energy storage device such as a backup capacitor to improve performance under various circumstances. The amount of power reserved for the APL may be dynamically determined based on various conditions of the memory system. The energy reserved for APL recovery may be dynamically budgeted so that excess energy from the energy storage device may be used to improve operations. The energy storage device may be recharged using surplus power when the amount of energy required for operations at the SSD is less than the maximum power budget for the SSD.
    Type: Grant
    Filed: July 23, 2024
    Date of Patent: June 2, 2026
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Louis Turmes
  • Patent number: 12638904
    Abstract: Applications are executed on a host in association with a power profile and a pool of one or more CPUs that are isolated relative to the applications. The power profile includes a lowest power state that is suitable for the applications and achieves required performance for the workload being performed by the applications. The applications may have fractional CPU requirements collectively met by the number of CPUs in the pool. Other components, such as the operating system and one or more agents of one or more orchestrators may be allocated their own isolated pool of CPUs operating at a highest power state. The implementation of isolated CPUs that are shared by multiple applications may be performed by an agent of an orchestrator that is called as the CRI when instantiating containers.
    Type: Grant
    Filed: March 28, 2024
    Date of Patent: May 26, 2026
    Assignee: Rakuten Symphony, Inc.
    Inventors: Sree Nandan Atur, Mruthyunjaya Navali, Ayushi Nikhil Patani, Nikhil Rohidas Gawade, Tushar Doshi
  • Patent number: 12638905
    Abstract: Systems and methods are provided for implementing mobile connectivity device wake detection and diagnosis. After detecting that a mobile connectivity device on a device has been awakened, an operating system (“OS”) control message support driver running on an OS determines a cause of awakening of the mobile connectivity device. The determined cause of awakening of the mobile connectivity device includes one of a control path reason, a firmware-based reason, a data path reason, or a peripheral component interconnect (“PCI”) bus-based reason. Based on each of these determined causes of awakening of the mobile connectivity device, a corresponding report (e.g., a control path wake reason report, a firmware-based wake reason report, a data path wake reason report, or a PCI bus-based wake reason report) is sent for further action (e.g., analysis of the wake reasons for subsequent system updates or patches to address the underlying issues associated with the wake reasons).
    Type: Grant
    Filed: June 28, 2024
    Date of Patent: May 26, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Yang You
  • Patent number: 12632101
    Abstract: The present disclosure is related to power control mechanisms for workload processing systems, and in particular, multi-scale power control technologies that can be used to reduce the overhead of workload processing systems. The disclosed power control mechanisms operate on multiple timescales including a slow timescale and a fast timescale. Separate control loops (or governors) are used for the slow and fast timescales where each control loop includes its own trigger mechanisms and configurable operational policies. The operational policies for slow timescale control loop can be trained separately using various machine learning techniques while the operational policies for the fast timescale control loop can be simple and reactive heuristics.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 19, 2026
    Assignee: Intel Corporation
    Inventors: Jaroslaw J. Sydir, Bin Li, Christopher MacNamara, David Hunt
  • Patent number: 12632098
    Abstract: A mobile communication device including a processor configured to obtain a data packet scheduling information; determine a computation load of a packet processing pipeline based on the data packet scheduling information; generate a power consumption profile of the processor based on the computation load; and control a plurality of cores of the processor based on the power consumption profile.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 19, 2026
    Assignee: Intel Corporation
    Inventors: Sumesh Subramanian, Thushara Hewavithana, Chengyu Liu
  • Patent number: 12632095
    Abstract: A method for power control includes receiving first power consumption data of a first compute device based on measurements of the first compute device, and receiving second power consumption data of a second compute device based on measurements of the second compute device. The method further includes receiving system power data to obtain a system power limitation. The method also includes calculating a power budget threshold for the first compute device and the second compute device based on the first power consumption data, the second power consumption data, and the system power limitation. The method includes controlling performance of the first compute device to operate within the power budget threshold, and controlling performance of the second compute device to operate within the power budget threshold.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: May 19, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Ronald Alton, Louis Louie, Chandan Agarwalla
  • Patent number: 12613568
    Abstract: This disclosure provides systems, methods, and devices for power state transitions with multiple chiplets. In a first aspect, a method of image processing includes receiving an indication to enter a partial sleep state for a processor comprising a first main domain and a first separate domain coupled through a different power supply path than the first main domain; and in response to the indication, transitioning, by the processor, the first main domain to a sleep state while the first separate domain remains in an active state for receiving processing requests or monitoring the first main domain. Other aspects and features are also claimed and described.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: April 28, 2026
    Assignee: QUALCOMM Incorporated
    Inventors: Shriharsha Chebbi, Lakshmi Narayana Panuku, Prashanth Kumar Kakkireni, Arun Gothekar, Anirudh Ghayal, Sriram Hariharan
  • Patent number: 12608480
    Abstract: A driver, e.g., a UEFI driver (140), for a device (120) in a host (110) starts before an OS boot. The driver (140) provides functions including gathering information regarding the host system (110), directing the device (120) to transmit the gathered information to a cloud-based service (182), directing the device (120) to provide a catalog of current firmware, updating firmware in the host (110) or device (120) based on the catalog, and configuring the device (120). The device may be a storage processing unit (120) that is part of a cluster (100) that presents virtual volumes including a boot volume (138) for the host (110), and execution of the driver (140) can provide a delay until a boot volume (138) is ready.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: April 21, 2026
    Assignee: Nvidia Corporation
    Inventors: Siamak Nazari, Dana Myers, Roopesh Tamma, Stuart Davies, William Price
  • Patent number: 12608038
    Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: April 21, 2026
    Assignee: Qualcomm Incorporated
    Inventors: Prashanth Kumar Kakkireni, Naveen Kumar Narala, Amod Phadke, Arun Gothekar, Anirudh Ghayal
  • Patent number: 12596423
    Abstract: A control method for an electronic device includes responding to a received first signal and sending a first trigger instruction when a first processor is in a first mode and responding to the received first signal and sending the first trigger instruction and a second trigger instruction when the first processor is in a second mode. The first rigger instruction is used to trigger a first event in an operating system. The second trigger instruction is used to trigger a second event in the operating system.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: April 7, 2026
    Assignee: LENOVO (BEIJING) LIMITED
    Inventor: Binqiang Ma
  • Patent number: 12596424
    Abstract: The present disclosure relates to a method for managing the deep sleep mode of an embedded system. In embodiments, the method includes determining a value of the electrical charge used, during a deep sleep mode of the system, for saving software-context data into a non-volatile memory of the system; determining a value of a current used, during a deep sleep mode of the system, for saving software-context data into a volatile memory of the system; determining, from the previously determined values, a threshold value defining a duration beyond which a power consumption caused by saving software-context data into the non-volatile memory is less than that into the volatile memory; saving the software-context data into the non-volatile or volatile memory according to the expected duration of deep sleep mode of the system.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: April 7, 2026
    Assignee: STMicroelectronics International N.V.
    Inventor: Stephane Le Coq
  • Patent number: 12596420
    Abstract: Systems, apparatuses and methods may provide for technology that configures a computing system to be a power sink from an external display, detects an alternating current (AC) power failure with respect to the external display, and configures the computing system to be a power source for the external display in response to the AC power failure. In one example, the technology places the external display in a low power state after the AC power failure is detected.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: April 7, 2026
    Assignee: Intel Corporation
    Inventors: Shailendra Singh Chauhan, Arunthathi Chandrabose, Ratheesh Nair, Arvind Tomar