Patents Examined by Y. Whang
  • Patent number: 5488542
    Abstract: The multichip module includes a ceramic multilayer substrate, a thick film wiring, a thick film insulator, a thin film multilayer wiring portion and semiconductor chips. The thick film wiring and the thick film insulator are laminated on the ceramic multilayer substrate. The thin film multilayer wiring portion is formed on the thick film insulator. In this thin film multilayer wiring portion, thin film wirings and thin film insulators are alternately laminated. The semiconductor chips are mounted on the thin film insulator of the thin film multilayer wiring portion, and the chips are electrically connected to a plurality of bonding pads made of the thin film wirings of the thin film multilayer wiring portion. A thick film wiring is situated underneath each bonding pad, and the thick film wiring is electrically connected to the thin film wiring in order to serve as a part of the wiring.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Ito
  • Patent number: 5488543
    Abstract: A frame stand for a device cabinet which has panels and serves in the installation of component carriers of industrial electronics. Four posts extend between a lower base plate and an identically-configured lid plate. To attach the panels, front brackets and rear brackets project from the base plate and the lid plate; these brackets are aligned with one another, and form recesses for cable harnesses.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: January 30, 1996
    Assignee: Schroff GmbH
    Inventors: Paul Mazura, Hans-Martin Schwenk
  • Patent number: 5483422
    Abstract: A guide mechanism prevents an improperly oriented PC card from being inserted a significant distance into a PC slot. A pair of PC card guide mechanisms are coupled to a PC male connector. A PC card is received at the guides as the card is inserted and pushed toward the male connector. Each guide mechanism includes a proximal end that engages an edge of the male connector, and a distal flanged end that receives the PC card. A guide rail extends between the proximal and distal ends of each guide mechanism. At least one guide mechanism includes a flexible arm along its guide rail. At the tip of the arm is a keying mechanism responsive to the PC card orientation. When the PC card is properly oriented, the card slides over the keying mechanism pushing it aside to traverse the guide rail. When the PC card is improperly oriented, the card is blocked by the keying mechanism so as not to traverse the guide rail.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: January 9, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Michael K. Bowen, Matt G. Driggers
  • Patent number: 5481438
    Abstract: Trays having the same size are piled up by fitting a downward extending edge frame formed on the whole periphery of the undersurface of each tray on the outer wall of the upward extending outer peripheral frame formed on the outer wall of the lower tray. The tray has multiple rectangular pockets defined by longitudinal and crosswise partition portions formed in a space defined by the inner wall of the outer peripheral frame. An upward projecting base is formed in the central portion of each pocket, for supporting the undersurface of a semiconductor device. Downward extending ribs are formed on the undersurface of each tray. Each rib surrounds upper side portions of the semiconductor device housed in the corresponding pocket of the lower tray and fitted on the inner wall of the inner wall of the lower tray. A first horizontal space D.sub.1 is defined between the outer peripheral frame and the edge frame, and a second horizontal space D.sub.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: January 2, 1996
    Assignee: Shinon Denkisangyo Kabushiki Kaisha
    Inventor: Hisashi Nemoto
  • Patent number: 5479321
    Abstract: A shielded mounting rack has a shielding plate (11) on its rear, which shielding plate (11) covers the back-panel wiring and is provided with apertures (12) for shielded plug connectors (1) which can be plugged on at the rear. The latter are in each case provided with a shielding casing (3) which has feathered contact tongues (4) which make contact with circumferential ground contact pins (10) on a back-panel wiring board (8). The ground contact pins (10) project into the apertures (12) in the shielding plate (11) and are pressed, by the contact tongues (4), against its inner wall. As a consequence, a fine-meshed ground connection is produced between the plug connector (1), the shielding plate (11) and the back-panel wiring (8).
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: December 26, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Eduard Mair, Gundolf Milde, Peter Sedlmeier
  • Patent number: 5477418
    Abstract: A connector system for an add in PC card for supplying network communications functions to a host computer wherein the connector to the network is a RJ type universal jack consisting of a socket and plug. A cavity in the card is formed by an opening in the short dimension of the frame opposite the 68 position connector and the top and bottom covers. A carriage is mounted in the cavity so that it can slide in and out and occupy at least two positions. The carriage consists of a socket portion for making contact with the RJ type plug and a support and contact portion that mechanically supports the carriage within the card and also makes the electrical contact between the carriage and the card. In the first of the two positions, substantially all of the carriage is within the cavity. In the second of the two positions, the socket portion of the carriage is outside of the cavity. In this position, the socket is electrically connected to the printed circuit board.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: December 19, 1995
    Assignee: Intel Corporation
    Inventors: Duncan D. MacGregor, Neal E. Broadbent, Chengwu Chen, Richard Gargiulo
  • Patent number: 5477419
    Abstract: A method of mounting an electronic part having a terminal portion on a board on which a circuit including a connection portion is formed. It includes a process of forming a conductive layer on the surface of the terminal portion; a process of forming, on the surface of the connection portion, a conductive layer having a melting point different from that of the conductive layer formed on the surface of the terminal portion; and a process of melting the conductive layer having a low melting point in such a state that the conductive layer of the terminal portion is contacted with the conductive layer of the connection portion, thereby fusing the conductive layer having a low melting point onto the conductive layer having a high melting point.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: December 19, 1995
    Assignee: Sony Corporation
    Inventors: Thomas W. Goodman, Hiroyuki Fujita, Yoshikazu Murakami, Arthur T. Murphy
  • Patent number: 5475569
    Abstract: An electronic package that is tested before the leads of the package are cut and bent into a final shape. The electronic package has a plurality of leads that extend from an outer housing of the package. The package is typically rectangular in shape and has a group of leads extending from each side of the housing. Extending along each group of leads is a strip of dielectric material that is spaced an offset distance from the side of the housing. The package is tested by placing a plurality of corresponding test pins into contact with the leads over their final cut and formed length in an area between the housing and the dielectric strip. The area of contact corresponds to the ends of the final assembled leads, so that the actual impedance of the leads over their final cut and formed length are tested. The dielectric strip provides structural support for the leads during the handling and testing of the package.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: December 12, 1995
    Assignee: Intel Corporation
    Inventors: Praveen Jain, Steve Prough
  • Patent number: 5475567
    Abstract: A method is provided for hermetically sealing a surface-mounted thick film electronic module within a cover soldered to a ceramic substrate, under the circumstances in which the input/output terminals of the electronic module are electrically interconnected with their corresponding external conductors on the exterior of the cover with a number of conductors. The integrity of the hermetic seal is promoted by routing the conductors beneath the ceramic substrate, as opposed to printing the conductors directly on the surface of the ceramic substrate, which necessitates that a dielectric material be placed intermediate the conductors and the bond material so as to electrically isolate the conductors from the bond material and cover. Consequently, an advantage of the present invention is the avoidance of a material mismatch between the dielectric material and the bonding material and the cover.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: December 12, 1995
    Assignee: Delco Electronics Corp.
    Inventor: John A. Hearn
  • Patent number: 5473512
    Abstract: An electronic device, such as an integrated circuit chip or a multichip module, is held in place overlying a circuit board, with which it is thermal expansion mismatched, by three or more localized rigid support elements. The bottom surface of the chip is bonded to the top surface of preferably only one of these support elements and can laterally slide along the top surfaces of the others in response to heating and cooling during electrical operations of the electronic device. In addition, the electronic device is encapsulated in a soft gel that is held in place by a rigid plastic half-shell cover that is epoxy-bonded in place along its perimeter (edge).
    Type: Grant
    Filed: June 16, 1994
    Date of Patent: December 5, 1995
    Assignee: AT&T Corp.
    Inventors: Yinon Degani, Thomas D. Dudderar, Byung J. Han, Venkataram R. Raju
  • Patent number: 5471368
    Abstract: A direct chip attach module (DCAM) 10, comprises of one or more electronic components 30, electrically bonded to a printed circuit 40, on a substrate 20. The DCAM 10, is bonded to an electronic circuit assembly by connection pads 50, formed on the edge of the DCAM substrate 10. This enables easy visual inspection of solder joints between the DCAM and the assembly. DCAM substrates 10, are initially formed in a panel form 70, and vias 50, are drilled and filled with electrically conductive media 55, at predetermined connection points. The DCAM 10, is then excised from the parent panel 70, and the cut vias provide connection pads 55, along the edge of the substrate 10.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: November 28, 1995
    Assignee: International Business Machines Corporation
    Inventors: Alan P. Downie, Peter Gallagher, John J. Garrity, Brian L. Robertson
  • Patent number: 5469335
    Abstract: A power distribution system and a method for supplying power to a first circuit board having a first contact member conductively mounted thereto and a first aperture through the first contact member substantially coaxially aligned with a first opening through the first circuit board is provided by the present invention. The system comprises an elongated conductive rod that is removably positioned through the first aperture and the first opening and that extends normally from the first circuit board. The rod is electrically connectable to the first circuit board by a first contact member and has a length sufficient to (a) enter a second aperture of a second contact member conductively mounted on a second circuit board parallel to and adjacent one side of the first circuit board and (b) contact a power connector adjacent an opposite side of the first circuit board to thereby allow the rod to distribute electrical current to multiple circuit boards.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: November 21, 1995
    Assignee: Compaq Computer Corporation
    Inventors: Michael R. Kluth, Roberta M. Reents
  • Patent number: 5467252
    Abstract: Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: November 14, 1995
    Assignee: Motorola, Inc.
    Inventors: Victor Nomi, John R. Pastore, Twila J. Reeves
  • Patent number: 5467253
    Abstract: A semiconductor device having a substrate support (22) and a method of forming the semiconductor device. A substrate (11) has conductive traces (12) and a bonding pad (13) on a bottom surface and conductive traces (14) and a semiconductor chip attach pad (17) on a top surface. The substrate support (22) has an aperture (23) and is coupled to the substrate (11). A semiconductor chip (31) is coupled to the semiconductor chip attach pad (17). The semiconductor chip (31) is covered by an encapsulating material (38) or a cap (41, 51) which provide protection for the semiconductor chip (31).
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: November 14, 1995
    Assignee: Motorola, Inc.
    Inventors: James K. Heckman, Francis J. Carney, Harry J. Geyer
  • Patent number: 5463531
    Abstract: An electronics housing that is compliant with a type II PCMCIA standard includes a frame (101) and coupled thereto a first and a second cover (103, 137), a connector (121) with a body (123) and a plurality of terminals (131), and a carrier (111) with a first side (113) and a second side (115). The first cover (103) includes an interior surface (105) with the carrier (111) disposed adjacent thereto and an interface surface (107). The body (123) is disposed adjacent to the interface surface (107) and includes a plurality of openings (129) extending through the body. The plurality of terminals (131) each includes a receptacle (133) and an integral contact (135) where the receptacle is disposed within the opening and the integral contact extends from the body and is formed to be mechanically coupled to the second side (115).
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: October 31, 1995
    Assignee: Motorola, Inc.
    Inventors: Low P. Choon, Brian Redman
  • Patent number: 5461544
    Abstract: A plurality of integrated circuit devices are bonded to a substrate. Signal traces for corresponding pins of the devices are run to the same location, but are not electrically connected. They are, however, located in close physical proximity at a designated location. At this designated location, a properly shaped and sized contact can be used to contact all of the corresponding traces simultaneously, allowing parallel burn-in of all devices on the substrate to be performed. The devices can still be tested individually after burn-in. Once functionality of the overall subsystem has been confirmed and encapsulation completed, a permanent contact can be made at the designated location to all traces simultaneously so that the devices will be in parallel, and the substrate can be encapsulated to form a completed subsystem.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: October 24, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Charles R. Ewers
  • Patent number: 5461545
    Abstract: According to an embodiment of the invention the discrete or integrated electronic components are encapsulated, each in a package, for example a plastic one; the packages are then mounted on a printed circuit board, for example an epoxy one. The components and board as a whole are covered with a relatively thick first layer consisting of an organic compound and ensuring a levelling function, followed by a second layer such as an inorganic metal compound, the function of which is to ensure the hermetic sealing of the whole.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: October 24, 1995
    Assignee: Thomson-CSF
    Inventors: Michel Leroy, Christian Val
  • Patent number: 5459643
    Abstract: An electrically enhanced wiring block with break test capability employs a printed circuit board which includes integrally defined transmission lines and capacitive elements designed to improve impedance characteristics and electrical balance between interconnected wiring and connecting strips and thereby optimize its transmission performance. The transmission lines consist of impedance controlled circuitry with integral capacitive elements that are provided by means of a novel use of plated through holes. The holes may be sized, spaced and interconnected in various configurations to generate the desired capacitance. Two rows of connecting blocks with a row of connecting strips therebetween are mounted to one side of the circuit board preferably by solderless connectors and are interconnected by circuitry on the circuit board. The capacitive elements are connected between selected leads of the connecting blocks and connecting strips by the impedance controlled circuitry.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: October 17, 1995
    Assignee: The Siemon Company
    Inventors: John Siemon, Howard Reynolds
  • Patent number: 5457608
    Abstract: A printed circuit board mounting apparatus for securing a printed circuit board within a chassis includes a track affixable to the chassis and a locking mechanism affixable to the printed circuit board. The track, which includes a plurality of locking points, is slidably received within the locking mechanism, which engages the track at any of the several locking points to secure the track within the locking mechanism. The mounting apparatus described herein enables the chassis to accommodate printed circuit boards of different sizes without mechanical modification of the chassis.
    Type: Grant
    Filed: October 28, 1993
    Date of Patent: October 10, 1995
    Assignee: Dell USA, L.P.
    Inventors: Erica Scholder, Karl Steffes, Robert Garrett
  • Patent number: 5457607
    Abstract: A transmit/receive (T/R) module of a phased array radar having a unified housing comprising an integrated connector as part of the module housing, thereby eliminating a hermetic joint between a group of DC signal pins and the module housing. Power and RF signal connector pins are provided in the housing. The pins of the connectors are inserted within the module housing with a glass compression seal around each pin.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: October 10, 1995
    Assignee: Raytheon Company
    Inventor: Ronald M. Carvalho