Abstract: An apparatus for address translation is provided in order to translate virtual addresses used by devices in a data processing system into physical addresses for accessing memory. In accordance with the techniques disclosed herein, state tracking circuitry is provided to maintain the state of a page table entry that specifies such address translations. The state can be used to assess whether or not the address translation entry is worth storing in an address translation cache provided for faster access of previously used address translations. Accordingly, the techniques disclosed herein allow for more efficient use of the limited capacity available in the address translation cache as well as additional uses of a page table entry's state.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a data merge operation; selecting a plurality of first-type physical units and a second-type physical unit from a rewritable non-volatile memory module to execute the data merge operation, wherein a data capacity of each first-type physical unit is less than a data capacity of each second-type physical unit; during a first execution period of the data merge operation, copying first data from a first physical unit in a stable state among the first-type physical units to the second-type physical unit; and during the first execution period, storing second data from a host system to a second physical unit not in the stable state among the first-type physical units.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for caching. The method includes determining whether a length of a to-be-processed token sequence is greater than a cache length threshold associated with a key-value (KV) data cache. The method further includes determining, in response to the length of the to-be-processed token sequence being greater than the cache length threshold, target KV data based on a token sequence exceeding the cache length threshold in the to-be-processed token sequence. In addition, the method further includes determining a target token based on the to-be-processed token sequence, the KV data cache, and the target KV data.

Abstract: A management system for managing a cache memory including a randomization module configured for generating a random value for each process of accessing the cache memory, and for transforming addresses of the cache memory with said random value into randomized addresses, a history table configured to store therein on each line an identification pair associating a random value corresponding to an access process, with an identifier of the corresponding access process, so forming identification pairs that are operative to dynamically partition the cache memory while registering the access to the cache memory, and a state machine configured to manage each process of accessing the cache memory according to the identification pairs stored in the history table.

Abstract: The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermedi

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

Abstract: A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

Abstract: A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.

Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

Abstract: Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.

Abstract: A SSD device comprising a plurality of memory cells programmable and readable at memory page level, and a controller for storing at least one table associated with a memory page. Each table comprises a plurality of table entries each one associated with a range of program/erase cycles and/or a range of retention times, and within each table entry optimal reference voltages indicative of the reference voltages to be used during the read operation of the memory page when the program/erase cycle and/or the retention time of the memory page fall within the range associated with the table entry. During a characterization of the SSD device, the optimal reference voltages are selected, for each range, among first candidate reference voltages indicative of the reference voltages at which the memory page falling within said range is successfully read, and second candidate reference voltages indicative of the reference voltages at which the memory page falling within at least one adjacent range is successfully read.

Abstract: A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

Abstract: The present disclosure provides a writing method, including: writing writing-table data into a corresponding main storage module; performing a calculation on writing-table data in each target main storage module by using a first predetermined algorithm to obtain an auxiliary value, for any target main storage module, the first predetermined algorithm being used for performing a calculation on writing-table data stored in the target main storage module and corresponding writing-table data stored in at least one main storage module other than the target main storage module, an inverse operation of the first predetermined algorithm being used for performing a calculation on any auxiliary value to obtain writing-table data participating in the calculation of the auxiliary value; and storing the auxiliary value into a corresponding auxiliary storage module. The present disclosure further provides a reading method, a computer readable storage medium, a processor chip and an electronic device.

Abstract: A system and method for managing queues for persistent storage. In some embodiments, the method includes opening, by a first thread running in a host, a first storage object; and creating, by the host, in a memory of the host, a first block device queue, the first block device queue being dedicated to the first storage object.

Abstract: A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.

Abstract: The disclosed technology relates to determining physical zone data within a zoned namespace solid state drive (SSD), associated with logical zone data included in a first received input-output operation based on a mapping data structure within a namespace of the zoned namespace SSD. A second input-output operation specific to the determined physical zone data is generated wherein the second input-output operation and the received input-output operation is of a same type. The generated second input-output operation is completed using the determined physical zone data within the zoned namespace SSD.

Abstract: Virtual memory pooling, including identifying GPUs of respective IHSs, wherein each of the GPUs is associated with a respective internal memory allocation; partitioning, for each GPU, the internal memory allocation associated with the GPU into a first memory allocation and a second memory allocation; allocating, for each GPU, the first memory allocation of the internal memory allocation associated with the GPU as accessible only by the associated GPU; pooling, for each GPU, the second memory allocation of the internal memory allocation associated with the GPU to define a virtual memory pool, the virtual memory pool accessible by each GPU; processing, at a first GPU, a computational task, including: accessing the first memory allocation associated with the first GPU; determining that processing of the computational task exceeds a capacity of the first memory allocation of the first GPU and in response, requesting access to the virtual memory pool.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. A computer program product and computer system are also disclosed.