Abstract: A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.

Abstract: The present disclosure involves methods, apparatuses, systems, and computer-readable storage media for processing memory controller commands in a memory system, and in particular, for processing unmap commands. In one example, a method for operating a memory system includes receiving, from a host, an unmap command corresponding to one or more logical addresses. The method further includes, in response to determining that a quantity of the one or more logical addresses is less than or equal to a first threshold, storing the one or more logical addresses in a buffer of a memory controller of the memory system. The method further includes updating a mapping table based on logical addresses stored in the buffer to unmap a mapping relationship between the logical addresses and corresponding physical addresses in the mapping table. The logical addresses stored in the buffer correspond to more than one unmap command.

Abstract: Recovering worker shares from read prioritization including: while read accesses (RA) to a storage device (SD) are being prioritized over write accesses (WA) to the SD: determining a first count of RA to the SD; performing a first adjusting of a base read share percentage (RSP) to a first adjusted RSP for RA to the SD based on the first count of RA; and controlling read access to the SD based on the first adjusting; determining that RA to the SD have completed being prioritized over WA to the SD; and after RA to the SD have completed being prioritized: determining a second count of WA to the SD; performing a second adjusting of the first adjusted RSP to a second adjusted RSP for RA to the SD based on the second count of WA; and controlling write access to the SD based on the second adjusting.

Abstract: A storage controller, a data reading method and a storage device. data reading method: identifying a plurality of logical addresses corresponding to files based on file read commands; determining a plurality of mapping tables corresponding to files based on logical addresses; loading a first mapping table corresponding to a first file to a first memory section of a buffer memory; identifying one or more second logical addresses of one or more second files corresponding to first mapping table among files or than first file; determining target content of first mapping table based on one or more second logical addresses, and copying target content to a second memory section of buffer memory; and from target content, finding a fourth physical address corresponding to a fourth logical address of a fourth file among second files, to read fourth data of fourth file, so as to respond to a fourth file read command.

Abstract: Examples of the present application provide a memory device, memory system, memory controller and operating method thereof, wherein the memory device includes: an array of memory cells, including multiple memory cells, and a preset number of memory cells forming one code word; peripheral circuit coupled to the array of memory cells and configured to: generate a first boundary voltage and a second boundary voltage in accordance with the first result corresponding to at least one code word at a target read voltage; make at least one adjustment to the target read voltage, and obtain the corresponding first result at the adjusted target read voltage after each adjustment; in a process of the adjustment, change a current direction of adjustment to the voltage in accordance with the target read voltage after one adjustment exceeding a range defined by the first boundary voltage and the second boundary voltage.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

Abstract: A method of operating a controller includes sensing power-on of a memory system including a semiconductor memory device, determining whether to delay a garbage collection operation performed during an initial operation of the memory system, based on a sudden-power off (SPO) count value, and controlling the semiconductor memory device to perform the garbage collection operation based on the determination result.

Abstract: In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.

Abstract: As described herein, a system, method, and computer program are provided for batching a collection of elements in local memory for processing. A single collection of elements of data is stored in a local memory across a plurality of sub-collections. The single collection of elements is processed on a sub-collection basis, where each sub-collection is removed from the local memory upon completion of the processing of the elements in the sub-collection.

Abstract: A system for secured computing comprises: an interconnect; a processing element communicatively connected to the interconnect; and a memory controller communicatively connected to the interconnect and to a memory; wherein access of a memory block by the memory controller to and from the interconnect is accompanied by a security class of a plurality of security classes; wherein each memory block is associated with a security class assigned to the content stored in the memory block from amongst a plurality of security classes; wherein the associated security class of each memory block travels in the system together with the content of the associated memory block; wherein the memory controller employs at least one matrix; and wherein the at least one matrix defines interactions between the security classes of memory blocks of content as the content of the memory blocks which are being handled by at least the memory controller.

Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.

Abstract: A transaction method includes initializing a first read counter according to a first predefined read count by a microcontroller unit (MCU), writing data to a cache by a first processing element, reading the data from the cache by a second processing element, transmitting a first read done message from the second processing element to the MCU after the data of the cache is read by the second processing element, decrementing the first read counter according to the first read done message by the MCU, and transmitting a first frame-discard cache maintenance operations (CMO) command from the MCU to the cache when the first read counter is decremented to zero.

Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

Abstract: A data storage device includes a bandwidth balancing system operable to reduce or eliminate bandwidth availability fluctuations that occur as a result of the performance of various internal operations and host operations. The bandwidth balancing system reduces or eliminates bandwidth availability fluctuations using a randomness factor. The randomness factor is a value that indicates a probability that an entire memory block will be invalidated by a single operation, which would cause the validity count of the memory block to significantly drop, thereby causing bandwidth availability fluctuations. The bandwidth balancing system ensures the memory blocks have a desired randomness factor by enabling the memory blocks to store both random data and sequential data. Specifically, the bandwidth balancing system intelligently mixes random data and sequential data within a memory block to achieve the desired randomness factor.

Abstract: Instead of waiting for a write command to complete, a coherency table in a solid state drive (SSD) will expedite the read command start time. The coherency table allows a response to the write command will be sent to the host as soon as a write command is received. The coherency table will continue to process the write command through to the encryption/decryption (XTS) module and then over to the DRAM as normal. Once the read command reaches the coherency table, the command will be assessed for any issues. If there is an issue detected, then the coherency table will delay the read command until the previous write command reaches the DRAM (after going through the XTS module). Once the data from the write command reaches the DRAM the coherency table is cleared, and the read command is no longer delayed. The data can now be read from DRAM, decrypted in the XTS module and sent back to the host. Data is encrypted due to the write command before being sent to the DRAM.

Abstract: A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Abstract: Embodiments control garbage collection priority based on both a local memory pressure and a global memory pressure. The local pressure represents volatile memory usage in a container or other isolation unit residing on a machine, and the global pressure represents volatile memory usage in the machine overall. The machine is a device or a virtual machine containing one or more isolation units. Each isolation unit has a low threshold and a high threshold, and the machine has its own low threshold and its own high threshold. Garbage collection execution priority is set to low, normal, or high, depending on the memory pressures and the thresholds. By basing garbage collection timing and performance on both local pressure and global pressure, embodiments optimize garbage collection efficiency, especially in memory overcommitment scenarios.

Abstract: The present disclosure provides a memory programming method, a memory device and a memory system. The memory device comprises a plurality of memory cells. The method comprises: performing a first incremental step pulse programming on the memory cells; performing a first programmed state verification on the memory cells; and performing a second incremental step pulse programming on the memory cells, comprising: determining an incremental voltage in the second incremental step pulse programming being less than a default incremental voltage, in response to a programming temperature of the memory cells being within a preset first temperature range. Implementations of the present disclosure can improve read margin of the memory cells, reduce read errors, and reduce overall loss for the performance of the memory device.

Abstract: A computer-readable recording medium having stored therein a program causes one of processors to execute a process including: upon controlling an access from each of the processors to a shared memory including a storage area shared among the processors, determining the number of one or more first processors that can be controlled by hardware when the access is to be controlled by the hardware; and performing, based on a frequency of the access to the shared memory from the processors, a control of the access to the shared memory from a second processor, the number of one or more second processors being excluded the determined number of the first processors from the processors, by a first control being performed by software executed by the second processor, or by a second control being performed by the first processor according to a command issued by the second processor.

Abstract: A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.