Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.

Abstract: The present technology includes a controller and a memory system including the same. The controller includes a descriptor manager configured to generate descriptors including logical addresses and physical addresses respectively mapped to the logical addresses, a map cache configured to store the descriptors in a linear structure and a binary tree structure, and a map search engine configured to search for a descriptor corresponding to a logical address received from an external device among the descriptors stored in the map cache by performing a linear search method, a binary search method, or both, according to a status of the map cache.

Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

Abstract: Techniques for providing effective utilization of different drive capacities in storage appliances. The techniques include providing a storage drive array that has a first set of storage drives and a second set of storage drives. Each storage drive in the first set has a first drive capacity and each storage drive in the second set has a second drive capacity. The first drive capacity is higher than the second drive capacity. The techniques include allocating, within the first drive capacity, at least a first sub-capacity and a second sub-capacity. The first sub-capacity is equal to the second drive capacity. The techniques include placing blocks of hot data in the first sub-capacities of the storage drives in the first set and/or the second drive capacities of the storage drives in the second set, and placing blocks of cold data in the second sub-capacities of the storage drives in the first set.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.

Abstract: Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and/or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: Techniques for encrypted-data-only media operations are described. In some instances, data from a source to be written to memory of a storage device is received by a storage device and the storage devices determines whether the data is encrypted at a storage location based on an amount of entropy of the received data. When the received data is not encrypted a media error is returned to the source and when the received data is encrypted the data is written.

Abstract: System and techniques for memory side cache request handling are described herein. When a memory request is received, a cache set for the memory request is determined. Here, the cache set has multiple ways and each way corresponds to a cache line. It can be detected that a way of the multiple ways is not ready for the memory request. In this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. Entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. The defined order gives priority to memory requests for a present way and then for external over internal requests.

Abstract: A processor receives, from an input device, input data for processing. Upon determining that the input data corresponds to an artificial intelligence (AI) application, the processor generates an AI command for performing read or write operations for a memory device that is configured to store data for a plurality of applications including the AI application, the AI command characterized by an operational code and including information about one or more components of the AI application corresponding to the input data. The processor sends the AI command and the input data to a storage controller managing the memory device, wherein the read or write operations for the memory device are performed by the storage controller using the operational code and the information included in the AI command. The processor receives, from the storage controller, a result of the read or write operations performed on the memory device.

Abstract: Aspects of the invention include identifying a first subsystem and a second subsystem of a plurality of subsystems respectively storing a first compressed data and a second compressed data, wherein the first compressed data and the second compressed data are fragments of a requested data. A compression method used to compress the first compressed data and second compressed data is identified. A first accelerator of first subsystem and a second accelerator of the second subsystem is identified. The first compressed data from a first local memory of the first subsystem is offloaded to the first accelerator, and the second compressed data from a second local memory of the second subsystem is offloaded to the second accelerator, wherein offloading comprises provided a decompression method for the first compressed data and the second compressed data.

Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.

Abstract: A method for execution by a storage unit in a dispersed storage network (DSN) includes selecting a storage zone of a memory device of the storage unit based on zone allocation parameters, and designating the selected storage zone as open for writes. A data slice is received via a network for storage. The data slice is written sequentially at a memory location of the one of storage zone based on determining that the storage zone is designated as open for writes. A pointer corresponding to the data slice that indicates the storage zone and the memory location is generated. A read request is received via the network from a requesting entity that indicates the data slice. The data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.

Abstract: An interprocess communication (IPC) method and an IPC system for transmit communication data from a first process to a second process, where the method includes performing initialization configuration on the first process and the second process, including creating first memory space in shared memory space, selecting a communication manner based on a length of the communication data and a value of a threshold, where the threshold is a size of the first memory space, performing interprocess data exchange in the selected communication manner, selecting a memory sharing manner for communication when the length of the communication data is less than the threshold, and selecting a data file manner for communication when the length of the communication data reaches or exceeds the threshold.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

Abstract: According to one embodiment, a storage system includes a network interface controller, a volatile memory and a storage device. The network interface controller is configured to communicate with a client using remote direct memory access. The network interface controller is configured to store write data and a submission queue entry including a write request of the write data transferred using the remote direct memory access in the volatile memory. The storage device is configured to write, when the submission queue entry is stored in a submission queue of the volatile memory, the write data to the storage device based on the submission queue entry.