Patents Examined by Yaima Rigol
  • Patent number: 12007888
    Abstract: Methods, systems, and devices for techniques to group media blocks are described. In some cases, a computing system may generate a memory map for a preconfigured size or chunk of data. For example, the computing system may divide files of media blocks into a set of fixed sized chunks of consecutive media blocks. Upon an application requesting a memory map for a set of media blocks, a storage layer of the computing system may generate a sub-map of the memory map for each chunk of data containing a media block of the set of requested media blocks. In some cases, the computing system may assign the chunks of data a continuous range of addresses in the virtual address space of the application. Upon generating the memory map, the storage layer may return an indication of the virtual address ranges of the requested media blocks to the application.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: June 11, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Nabeel Meeramohideen Mohamed, Greg Alan Becker, Steven Andrew Moyer
  • Patent number: 12007891
    Abstract: Technology for enabling a kernel to perform data deduplication on encrypted storage of a container. An example method may involve: enabling, by a kernel, a guest program of a container to access a first storage block of a first container and a second storage block of a second container; receiving, by the kernel from the guest program, an indication that the first storage block and the second storage block are duplicate storage blocks; and updating the first storage block or the second storage block to cause the duplicate storage blocks to reference a common storage location.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: June 11, 2024
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 12001336
    Abstract: A memory device includes a page buffer with a cache register and data registers, a memory array with a set of sub-blocks of memory cells configured as single-level cell (SLC) memory, and control logic. The control logic performs operations including: causing a first page of SLC data to be stored in the cache register; causing the first page of the SLC data to be moved from the cache register to a first data register; causing a subsequent page of the SLC data to be stored in the cache register; causing the SLC data stored in the cache register and in the data registers to be concurrently programmed to the set of sub-blocks, where the first page is programmed to a first sub-block and the subsequent page is programmed to a subsequent sub-block; and causing a subset of the operations for programming the set of sub-blocks to be performed in parallel.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Siciliani, Violante Moschiano, Walter Di Francesco
  • Patent number: 12001717
    Abstract: Implementations described herein relate to memory device operations for unaligned write operations. In some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. The memory device may allocate a set of buffers for the write command. The memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. The memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. The memory device may write the data unit to memory indicated by the set of physical addresses.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Scheheresade Virani
  • Patent number: 11994988
    Abstract: Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: May 28, 2024
    Assignee: OPEN TEXT INC.
    Inventor: John R. Shaw, II
  • Patent number: 11994992
    Abstract: Provided is a takeover method for cache partition recovery, including: determining whether a cluster has a four-controller topology, and when having the four-controller topology, setting a four-controller topology flag for each cache partition of the cluster; in response to monitoring that the cluster is changed to a cluster having a dual-controller topology and including a first node and a second node, determining whether a third node and a fourth node that exit the cluster belong to a same sub-cluster, and when belonging to the same sub-cluster, further determining whether cache partitions of the sub-cluster are set with the four-controller topology flag; and when set with the four-controller topology flag, further determining whether the sub-cluster is in a single-partition mode or dual-partition mode, and respectively taking over, by the first node and the second node, the third node and the fourth node based on the single-partition mode or dual-partition mode.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: May 28, 2024
    Assignee: SHANDONG YINGXIN COMPUTER TECHNOLOGIES CO., LTD.
    Inventors: Hongsheng Hou, Wenzhi Liu
  • Patent number: 11983416
    Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Patent number: 11983118
    Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 14, 2024
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Qiang Li, Yi Li, Liangliang Niu, Dongjie Tang, Yongjian Lv
  • Patent number: 11983119
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11977499
    Abstract: Generally disclosed herein is a hardware/software interface for asynchronous data movement between an off-core memory and a core-local memory, referred to as “stream transfers”, and a stream ordering model. The stream transfers allow software to more efficiently express common data-movement patterns, specifically ones seen in sparse workloads. Direct stream instructions that belong to a stream are processed in-order. For indirect stream instructions, offset elements in an offset list are processed in order. A sync flag is updated to indicate monotonic incremental progress for the stream.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 7, 2024
    Assignee: Google LLC
    Inventors: Rahul Nagarajan, Arpith Chacko Jacob, Suvinay Subramanian, Hema Hariharan
  • Patent number: 11972152
    Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: April 30, 2024
    Inventors: Patrick A. La Fratta, Robert Walker
  • Patent number: 11972143
    Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 30, 2024
    Assignee: Apple Inc.
    Inventors: Matthew J. Byom, Tudor Antoniu, Alexander Paley, Andrew W. Vogan, Muhammad N. Ashraf
  • Patent number: 11972135
    Abstract: A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: April 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Eric N. Lee, Dheeraj Srinivasan
  • Patent number: 11960754
    Abstract: A logical array having a plurality of memory banks is constructed, wherein each of the plurality of memory banks is split into a plurality of slots. A plurality of elements corresponding to a plurality of data components are stored in the plurality of slots of each of the plurality of memory banks of the logical array. The location of a data component stored in the memory component is determined by locating elements stored in a particular slot of the plurality of slots; and performing a corrective search on the located elements in the particular slot to locate a particular element. The data component is accessed based on the location of the particular element.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Revanth Kamaraj, Brian Toronyi, Balwinder Pal Sethi, Trapti Jain, Madhu, Chandrakanth Rapalli
  • Patent number: 11954041
    Abstract: The present technology includes a controller and a memory system including the same. The controller includes a descriptor manager configured to generate descriptors including logical addresses and physical addresses respectively mapped to the logical addresses, a map cache configured to store the descriptors in a linear structure and a binary tree structure, and a map search engine configured to search for a descriptor corresponding to a logical address received from an external device among the descriptors stored in the map cache by performing a linear search method, a binary search method, or both, according to a status of the map cache.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Joung Young Lee
  • Patent number: 11947841
    Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Keun Soo Song, Hyunyoo Lee, Kang-Yong Kim
  • Patent number: 11947803
    Abstract: Techniques for providing effective utilization of different drive capacities in storage appliances. The techniques include providing a storage drive array that has a first set of storage drives and a second set of storage drives. Each storage drive in the first set has a first drive capacity and each storage drive in the second set has a second drive capacity. The first drive capacity is higher than the second drive capacity. The techniques include allocating, within the first drive capacity, at least a first sub-capacity and a second sub-capacity. The first sub-capacity is equal to the second drive capacity. The techniques include placing blocks of hot data in the first sub-capacities of the storage drives in the first set and/or the second drive capacities of the storage drives in the second set, and placing blocks of cold data in the second sub-capacities of the storage drives in the first set.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 2, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel E. Cummins, Vamsi K. Vankamamidi, Shuyu Lee
  • Patent number: 11947828
    Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: April 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu
  • Patent number: 11941254
    Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Patent number: 11940911
    Abstract: Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and/or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 26, 2024
    Assignee: NetApp, Inc.
    Inventors: Sudheer Kumar Vavilapalli, Asif Imtiyaz Pathan, Parag Sarfare, Nikhil Mattankot, Stephen Wu, Amit Borase