Patents Examined by Yaima Rigol
  • Patent number: 10761742
    Abstract: A method and system for dynamic redundancy in storage systems is described. The method may include receiving a data fragment from a data stream of user data to be archived. The method may further include splitting the data fragment into a first number of data chunks. The method may also include, in response to determining that the data fragment is not a last data fragment in the data stream, generating a second number of additional data chunks based upon, at least in part, the first number of data chunks. The method may additionally include, in response to determining that the data fragment is the last data fragment in the data stream, generating a third number of additional data chunks based upon, at least in part, the first number of data chunks.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 1, 2020
    Assignee: ACRONIS INTERNATIONAL GMBH
    Inventors: Andrey Neporada, Stanislav Protasov, Serguei M. Beloussov
  • Patent number: 10747432
    Abstract: A storage device includes a first memory having a first access speed, a second memory having a second access speed slower than the first access speed, and a processor coupled to the first memory and the second memory and configured to copy one or a plurality of first data blocks included in a plurality of data blocks stored in the first memory, to the second memory, determine whether a processing amount per unit of time in the first memory reaches a threshold value based on a limit value of the processing amount when the processor receives a read request of a second data block included in the first data blocks, and read the second data block from the first memory when the processing amount does not reach the threshold value, and read the second data block from the second memory when the processing amount reaches the threshold value.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 18, 2020
    Assignee: FUJITSU LIMIITED
    Inventors: Hiroki Kimura, Toshiharu Makida
  • Patent number: 10740038
    Abstract: Embodiments described herein are related to performing virtual application delivery. In some embodiments, a method includes accessing, at a computing device, a datastore comprising a first virtual disk file mapped to a plurality of virtual disk files separate from the first virtual disk file, wherein each of the plurality of virtual disk files comprises at least one application stored thereon. The method further includes receiving, at the computing device, one or more operations for accessing the first virtual disk file, the one or more operations corresponding to a first application stored on a second virtual disk file of the plurality of virtual disk files. The method further includes redirecting the one or more operations for accessing the first virtual disk file to the second virtual disk file.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 11, 2020
    Assignee: VMWARE, INC.
    Inventors: Michael John Wookey, Paul Adam Ryman, Maria Matelle Tarroza, Mallikharjuna Reddy Deva, Stephen Jonathan Parry-Barwick
  • Patent number: 10740171
    Abstract: In an information processing apparatus including a first memory storing data, whether the first memory is in a state where the stored data is readable and data is unwritable is determined. When it is determined that the first memory is in the state, whether particular data is stored in the first memory is determined. When it is determined that the particular data is stored in the first memory, whether a second memory is connected to the information processing apparatus is determined. When it is determined that the second memory is connected, the particular data is read from the first memory and is written into the second memory.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 11, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Atsushi Ikeda
  • Patent number: 10732866
    Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 10705744
    Abstract: A method, a data storage system, and a computer-readable recording medium for disk array data distribution are proposed. The method includes the following steps. The space of a disk array composed of multiple flash storage devices is divided into multiple RAID extents with a same data distribution pattern, where each of the RAID extents includes a first region having multiple first stripes and first strips and also a second region having multiple second stripes and second strips. The first strips in each of the first stripes are evenly distributed among the flash storage devices in a first rotation pattern, and the second strips in each of the second stripes are unevenly distributed among the flash storage devices in a second rotation pattern.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: July 7, 2020
    Assignee: QNAP SYSTEMS, INC.
    Inventor: Chin-Hsing Hsu
  • Patent number: 10705964
    Abstract: In one embodiment, a processor includes a control logic to determine whether to enable an incoming data block associated with a first priority to displace, in a cache memory coupled to the processor, a candidate victim data block associated with a second priority and stored in the cache memory, based at least in part on the first and second priorities, a first access history associated with the incoming data block and a second access history associated with the candidate victim data block. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Kshitij A. Doshi, Christopher J. Hughes
  • Patent number: 10705987
    Abstract: A control circuit for controlling memory prefetch requests to system level cache (SLC). The control circuit includes a circuit identifying memory access requests received at the system level cache (SLC), where each of the memory access requests includes an address (ANEXT) of memory to be accessed. Another circuit associates a tracker with each of the memory access streams. A further circuit performs tracking for the memory access streams by: when the status is tracking and the address (ANEXT) points to an interval between the current address (ACURR) and the last prefetched address (ALAST), issuing a prefetch request to the SLC; and when the status is tracking, and distance (ADIST) between the current address (ACURR) and the last prefetched address (ALAST) is greater than a specified maximum prefetch for the associated tracker, waiting for further requests to control a prefetch process.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 7, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Arkadi Avrukin, Seungyoon Song, Tariq Afzal, Yongjae Hong, Michael Frank, Thomas Zou, Hoshik Kim, Jungsook Lee
  • Patent number: 10705979
    Abstract: An apparatus, method, program product, and system are disclosed for evicting pages from memory using a neural network. One embodiment of a method for evicting pages from memory using a neural network includes determining state information related to evicting pages from memory. The state information may be determined by a dedicated hardware snooping device that snoops a system bus for the state information. The method includes determining an identifier for a page in memory to be evicted using a neural network. The neural network performs machine learning operations on the state information to identify the page in memory to be evicted. The method includes locating the identified page in memory using the identifier determined by the neural network and evicting the identified page from memory.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Amanda A. Liem, Matthew R. Ochs, Lennard G. Streat, Brendan M. Wong
  • Patent number: 10698815
    Abstract: To provide enhanced operation of data storage devices and systems, various systems, apparatuses, methods, and software are provided herein. In a first example, a data storage device accumulates write data into a cache storage region prior to committing into an archive storage region and maintains a data structure that tracks the write data in the cache storage region. Responsive to receiving first write data into the cache storage region, the data storage device establishes first tracking elements in the data structure for the first write data in the cache storage region. Responsive to receiving second write data directed to storage locations overlapping the first write data, the data storage device accepts the second write data into the cache storage region and establishes second tracking elements in the data structure for the second write data in the cache storage region without modifying the first tracking elements.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 30, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Randall L. Hess, Berck E. Nash, James M. Reiser, Randy L. Roberson, Kris B. Stokes, Jesse L. Yandell
  • Patent number: 10691554
    Abstract: Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store copies of network-accessible block data storage volumes that may be used by programs executing on other physical computing systems, and snapshot copies of some volumes may also be stored (e.g., on remote archival storage systems). A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other computing systems at that data center, while the archival storage systems may be located outside the data center. The snapshot copies of volumes may be used in various ways, including to allow users to obtain their own copies of other users' volumes (e.g., for a fee).
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: June 23, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Peter N. DeSantis, Atle Normann Jorgensen, Matthew S. Garman, Tate Andrew Certain, Roland Paterson-Jones
  • Patent number: 10691375
    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Paolo Faraboschi, Daniel Gmach, Yuan Chen, Al Davis, Adit Madan
  • Patent number: 10678703
    Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the name portion to the logical addresses defined for the entire non-volatile storage media.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 10678470
    Abstract: Securing redundancy for physical storage devices that are extended in units smaller than physical storage devices configuring one RAID group. When d+r pieces of physical storage devices are connected by connecting r pieces of physical storage devices, a computer: adds v×r pieces of logical chunks; adds n×v pieces of physical storage areas in each additional storage device; changes mapping information to associate n pieces of physical storage areas with v×(d+r) pieces of logical chunks under a mapping condition; in response to a write request of user data, creates redundant data; determines a first logical chunk corresponding to the write request; and respectively writes n pieces of element data including the user data and the redundant data into n pieces of physical storage areas corresponding to the first logical chunk, based on the mapping information.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 9, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Takeru Chiba, Shintaro Ito, Mitsuo Hayasaka
  • Patent number: 10664201
    Abstract: Provided are a computer program product, system, and method for considering input/output workload and space usage at a plurality of logical devices to select one of the logical devices to use to store an object. A determination is made of a logical device to store the object based on workload scores for each of the logical devices indicating a level of read and write access of objects in the logical device and space usage of the logical devices. The object is written to the determined logical device.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Anglin, Arthur John Colvig, Michael G. Sisco
  • Patent number: 10643707
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a command from a device to perform a write operation at the non-volatile memory. The command indicates a plurality of logical addresses, data associated with the plurality of logical addresses, and a number of write operations associated with the command.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Thibash Rajamani, Ramesh Chander, Manavalan Krishnan, Brian O'Krafka, Nagi Reddy Chodem
  • Patent number: 10635314
    Abstract: A computer program product for implementing write procedures using an estimated best setting in a first run, the computer program product comprising a computer readable storage medium having program instructions executable by a tape drive to cause the tape drive to perform a method comprising: receiving, at the tape drive, a request for a write operation to be performed in the tape drive; determining, by the tape drive, a capacity margin ratio of the tape drive; determining an optimum a write procedure based at least in part on the capacity margin ratio; and invoking the optimum write procedure in response to determining the optimum write procedure. The optimum write procedure is selected from the group consisting of: a backhitch write procedure, a same wrap backhitchless flush (SWBF) write procedure, and a recursively accumulating backhitchless flush (RABF) write procedure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: James M. Karp, Takashi Katagiri, Yuhko Mori, Yutaka Oishi
  • Patent number: 10635536
    Abstract: A method for execution by a device of a dispersed storage network (DSN) to access a set of encoded data slices. The method begins by performing a first distributed agreement protocol (DAP) function using a slice identifier and a first set of coefficients to identify a set of storage units. The method continues by performing a second DAP function using the slice identifier and a second set of coefficients to identify pillar numbers for the set of storage units. The method continues by sending a set of data access requests to the set of storage units in accordance with the pillar numbers, wherein a data access request of the set of data access requests includes a slice name for a corresponding one of the set of encoded data slices and wherein the slice name includes one of the pillar numbers.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Wesley B. Leggette, Manish Motwani, Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10629255
    Abstract: A processing system and method for a data strobe signal (DQS). A counter circuit counts falling edges of the DQS within a valid region of the DQS and thereby generates a plurality of counting signals. An OR logic circuit receives the counting signals and a DQS window start signal and thereby generates a DQS window signal. A filter circuit is provided to gate the DQS according to the DQS window signal. The DQS window start signal is kept asserted until at least one of the counting signals changes due to the counting.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 21, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Chen Chen, Hui Wu, Fan Jiang, Qiang Si
  • Patent number: 10628279
    Abstract: To manage memory in a multi-processing system, a memory budget is assigned to each of a number of agents within the multi-processing system. A portion of memory is allocated to each the agents within the memory budget. Metrics are collected for each agent during processing of data by the agents; the metrics include an amount of data processed and an amount of memory used for each agent. Memory efficiency is determined for each agent based on the collected metrics and another memory budget is determined based on the memory efficiency. The portion of the memory is reallocated to the agents within the other memory budget in response to data stored in the memory relative to the assigned memory budget meeting a criterion.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gopi K. Attaluri, Ronald J. Barber, Vijayshankar Raman, Liping Zhang