Abstract: A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

Abstract: The present disclosure provides a writing method, including: writing writing-table data into a corresponding main storage module; performing a calculation on writing-table data in each target main storage module by using a first predetermined algorithm to obtain an auxiliary value, for any target main storage module, the first predetermined algorithm being used for performing a calculation on writing-table data stored in the target main storage module and corresponding writing-table data stored in at least one main storage module other than the target main storage module, an inverse operation of the first predetermined algorithm being used for performing a calculation on any auxiliary value to obtain writing-table data participating in the calculation of the auxiliary value; and storing the auxiliary value into a corresponding auxiliary storage module. The present disclosure further provides a reading method, a computer readable storage medium, a processor chip and an electronic device.

Abstract: A memory controller includes: a program operation controller configured to control a memory device to store data and individual mapping information; a mapping information storage configured to store therein mapping information; a mapping information update controller configured to control the memory device to store the mapping information in a second memory block; perform an update operation of updating the mapping information, and delay, when sequentiality of a predetermined number or more of logical addresses is maintained with respect to the predetermined time, the update operation until the sequentiality is broken; and a Sudden Power Off Recovery (SPOR) controller configured to receive the individual mapping information, recover the mapping information for the data stored in the page during a delay section and provide the recovered mapping information to the mapping information storage.

Abstract: A system and method for managing queues for persistent storage. In some embodiments, the method includes opening, by a first thread running in a host, a first storage object; and creating, by the host, in a memory of the host, a first block device queue, the first block device queue being dedicated to the first storage object.

Abstract: The disclosed technology relates to determining physical zone data within a zoned namespace solid state drive (SSD), associated with logical zone data included in a first received input-output operation based on a mapping data structure within a namespace of the zoned namespace SSD. A second input-output operation specific to the determined physical zone data is generated wherein the second input-output operation and the received input-output operation is of a same type. The generated second input-output operation is completed using the determined physical zone data within the zoned namespace SSD.

Abstract: Virtual memory pooling, including identifying GPUs of respective IHSs, wherein each of the GPUs is associated with a respective internal memory allocation; partitioning, for each GPU, the internal memory allocation associated with the GPU into a first memory allocation and a second memory allocation; allocating, for each GPU, the first memory allocation of the internal memory allocation associated with the GPU as accessible only by the associated GPU; pooling, for each GPU, the second memory allocation of the internal memory allocation associated with the GPU to define a virtual memory pool, the virtual memory pool accessible by each GPU; processing, at a first GPU, a computational task, including: accessing the first memory allocation associated with the first GPU; determining that processing of the computational task exceeds a capacity of the first memory allocation of the first GPU and in response, requesting access to the virtual memory pool.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Abstract: A system, method, and computer-program product includes implementing a cross-process queue within a single computer that is configured to transfer a data block between an operating system process executing a write operation and an operating system process executing a read operation, initializing in-memory cell indices within the cross-process queue that include a write operation index tracking index values of one or more cells within the cross-process queue that are available to write and a read operation index tracking index values of one or more cells within the cross-process queue that are available to read, and implementing a cell synchronization data structure tracking states of a plurality of cells of the index of cells of the cross-process queue.

Abstract: A computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. A computer program product and computer system are also disclosed.

Abstract: The present disclosure discloses a method and circuit for accessing a write data path of an on-chip storage control unit. The method includes: transmitting, by the write data path interface, the write address and the write data to an address conversion unit; transmitting, by the address conversion unit, a target address and the write data to a plurality of storage control units, and determining, by the address conversion unit, a target storage control unit; obtaining, by the address conversion unit, a feedback signal of the target storage control unit, and transmitting, by the address conversion unit, the feedback signal to the target controller; and storing the write data.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for migrating data in a data storage system. A method for migrating data comprises: transferring data from a storage cluster in a first data center to a migration cartridge of the first data center; converting, by the migration cartridge of the first data center, the data's format into an archival format; storing the data into a media card; and moving the media card from the first data center to a second data center, wherein the data is read from the media card into a migration cartridge of the second data center and stored into an archival cluster in the second data center according to the archival format of the data.

Abstract: A system, method, and computer-program product includes implementing a cross-process queue within a single computer that is configured to transfer a data block between an operating system process executing a write operation and an operating system process executing a read operation, initializing in-memory cell indices within the cross-process queue that include a write operation index tracking index values of one or more cells within the cross-process queue that are available to write and a read operation index tracking index values of one or more cells within the cross-process queue that are available to read, and implementing a cell synchronization data structure tracking states of a plurality of cells of the index of cells of the cross-process queue.

Abstract: A system includes a non-volatile memory device and a processing device to perform operations including creating a logical transfer unit (LTU) corresponding to a logical block address (LBA) received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA. The processing device comprises a hardware accelerator to perform operations comprising: retrieving, using an LTU identifier associated with the LTU, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space; and providing the metadata for use in determining and utilizing the physical address to perform a read operation specified by the read request.

Abstract: Provided is an apparatus and method for improving the entry speed of a large-memory consuming application in an electric device which detect an execution of an application, check if the application is a large-memory consuming application which uses a large amount of memory, and if the application is the large-memory consuming application, execute pre-process thread reclaim, select a process corresponding to a reclaiming target among processes currently resident in the memory, reclaim part of the memory being used by the selected process without terminating the selected process, and thereby improve the entry speed of a large-memory consuming application.

Abstract: A system including sensors of an advanced driver assistance system and a data recorder. The data recorder has: a volatile memory; a non-volatile memory configured with a file system region and a buffer region; and a processor configured to implement a file system mounted in the file system region. The data recorder records outputs from the sensors via the volatile memory into the buffer region in a cyclic way and, in response to an event, retrieve sensor data from the buffer region and store the sensor data into files organized under the file system mounted in the file system region.

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.

Abstract: The present technology relates to an electronic device. Based on the present technology, a storage device providing an improved security function may include a memory device including a protected memory block that is configured to store information for authenticating data to be read from or written to the memory device and is protected by a security protocol and a memory controller configured to receive a command protocol unit associated with the security protocol in a command including a host side protection message requesting data from a host be written in the protected memory block and perform a computation of a device message authentication code to be used in an authentication operation of the protected memory block, wherein the computation is performed concurrently with receiving a plurality of data units including the data from the host that is to be written in the protected memory block.

Abstract: Provided are ZNS standard based storage device providing data compression and method thereof. A provided method for processing an Input/Output (IO) command includes: providing, by a host to a storage device, a first command for writing data to a first storage zone; allocating, by the storage device according to a Write Pointer (WP) of the first storage zone, a first logical address index to the data to be written by the first command, wherein the first logical address index and a first size of the data to be written by the first command define a first logical address space; compressing the data to be written by the first command to obtain compressed data; storing the compressed data; recording an address for storing the compressed data in association with the first logical address index; providing the first logical address index to the host; and recording, by the host, a first host logical address (HLBA) accessed by the first command in association with the first logical address index.