Abstract: A memory management method, including: acquiring multiple architecture parameters of an artificial intelligence model; obtaining a memory allocation size used in a training process of the artificial intelligence model according to the multiple architecture parameters; configuring a target memory region in random access memory according to the memory allocation size, wherein train processing stage in the training process of the artificial intelligence model shares the target memory region; and temporarily storing intermediate data corresponding to each train processing stage of the training process of the artificial intelligence model in the target memory region, wherein the intermediate data is transferred between accelerator processor module, the random access memory, and a storage device. Thereby, the present invention can automatically calculate the optimized memory allocation size, and through the design of shared memory space, effectively improve memory fragmentation issues.

Abstract: Methods and systems for migrating data between provider systems are disclosed. The migration may be performed using a migration orchestrator as-a-service (MOaaS) schema where instances of a migration orchestrator that is configured at a data source (e.g., a source provider system) are instantiated on systems of all other actors/personas involved with the data migration. The instances of the migration orchestrator may cooperatively fulfill the migration of the data using a shared data migration transcript. Security vouchers containing share secrets may also be used to enhance security during migrations.

Abstract: A workload-based network-accessible memory pool provisioning system includes a computing device. A memory pool provisioning subsystem in the computing device identifies a workload type for a workload and, based on the workload type, configures a network-accessible memory pool using network-accessible memory devices coupled to the computing device via a network, and exposes the network-accessible memory pool for use in performing the workload. An operating system provided by the computing device uses the exposed network-accessible memory pool to perform the workload using a first subset of the network-accessible memory devices.

Abstract: A data erasure system (100) comprising a memory (101) comprising a plurality of banks (101a-n). The data erasure system (100) further comprises a processor (102) configured to write data to and/or read data from one of the plurality of banks (101a-n) at a time. The data erasure system (100) further comprises an erasure module (106) configured to perform an erasure operation by overwriting data on two or more of the plurality of banks (101a-n) concurrently, wherein overwriting data on one of the two or 10 more banks (101a-n) is independent of overwriting data on another of the two or more banks (101a-n).

Abstract: Aspects of the disclosed technology include techniques and mechanisms for using far memory telemetry for hot and cold page management. A processor within a telemetry system parses page access requests transmitted from a central processing unit (CPU) to a computing system. The processor parses the request to determine whether a directory contains a record for the requested page. Based on determining the directory does not store a record for the requested page and based on determining the directory is not at capacity, the processor generates a record and stores the record in the directory. The processor transmits a signal to the computing system to determine whether to perform one or more actions on the pages identified in the directory, such as move a page from a far memory device to a near memory device based on directory data indicating a number of access requests associated with each page.

Abstract: Apparatuses, systems, and techniques to facilitate storage allocation. In at least one embodiment, an application programming interface is used to execute instructions to cause storage to be allocated based on an indication of whether the storage may be modified.

Abstract: A storage system includes a host device and a storage device that are connected to each other through a main link and a sub link. The storage device includes a nonvolatile memory device configured to store data and a storage controller package configured to control the nonvolatile memory device under control of the host device. The storage controller package includes an on-chip bus, a host interface connected to the on-chip bus and the main link, a memory interface connected to the on-chip bus and the nonvolatile memory device, a storage processor connected to the on-chip bus, and configured to perform an in-band communication with the host device through the on-chip bus, the host interface and the main link, and a microcontroller connected to the on-chip bus and the sub link, and configured to perform an out-of-band communication with the host device through the sub link.

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

Abstract: Disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (DRAM)) that include a command/address inversion (CAI) input signal indicating whether command/address inputs to the memory devices are inverted. The CAI input signal may be generated by a memory controller, a registering clock driver (RCD), or other component coupled to the memory devices, and the component may generate the CAI input signal differently for the different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on the values of the command/address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.

Abstract: Systems and methods are disclosed for page table entry caches with multiple tag lengths. For example, an integrated circuit (e.g., a processor) includes a page table walk circuitry including a page table entry cache, in which the page table walk circuitry is configured to access a multi-level page table, and in which a first entry of the page table entry cache combines a first number of multiple levels and a second entry of the page table entry cache combines a second number of multiple levels that is different from the first number of multiple levels.

Abstract: A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.

Abstract: The present disclosure involves methods, apparatuses, systems, and computer-readable storage media for processing memory controller commands in a memory system, and in particular, for processing unmap commands. In one example, a method for operating a memory system includes receiving, from a host, an unmap command corresponding to one or more logical addresses. The method further includes, in response to determining that a quantity of the one or more logical addresses is less than or equal to a first threshold, storing the one or more logical addresses in a buffer of a memory controller of the memory system. The method further includes updating a mapping table based on logical addresses stored in the buffer to unmap a mapping relationship between the logical addresses and corresponding physical addresses in the mapping table. The logical addresses stored in the buffer correspond to more than one unmap command.

Abstract: Recovering worker shares from read prioritization including: while read accesses (RA) to a storage device (SD) are being prioritized over write accesses (WA) to the SD: determining a first count of RA to the SD; performing a first adjusting of a base read share percentage (RSP) to a first adjusted RSP for RA to the SD based on the first count of RA; and controlling read access to the SD based on the first adjusting; determining that RA to the SD have completed being prioritized over WA to the SD; and after RA to the SD have completed being prioritized: determining a second count of WA to the SD; performing a second adjusting of the first adjusted RSP to a second adjusted RSP for RA to the SD based on the second count of WA; and controlling write access to the SD based on the second adjusting.

Abstract: A storage controller, a data reading method and a storage device. data reading method: identifying a plurality of logical addresses corresponding to files based on file read commands; determining a plurality of mapping tables corresponding to files based on logical addresses; loading a first mapping table corresponding to a first file to a first memory section of a buffer memory; identifying one or more second logical addresses of one or more second files corresponding to first mapping table among files or than first file; determining target content of first mapping table based on one or more second logical addresses, and copying target content to a second memory section of buffer memory; and from target content, finding a fourth physical address corresponding to a fourth logical address of a fourth file among second files, to read fourth data of fourth file, so as to respond to a fourth file read command.

Abstract: Examples of the present application provide a memory device, memory system, memory controller and operating method thereof, wherein the memory device includes: an array of memory cells, including multiple memory cells, and a preset number of memory cells forming one code word; peripheral circuit coupled to the array of memory cells and configured to: generate a first boundary voltage and a second boundary voltage in accordance with the first result corresponding to at least one code word at a target read voltage; make at least one adjustment to the target read voltage, and obtain the corresponding first result at the adjusted target read voltage after each adjustment; in a process of the adjustment, change a current direction of adjustment to the voltage in accordance with the target read voltage after one adjustment exceeding a range defined by the first boundary voltage and the second boundary voltage.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

Abstract: A method of operating a controller includes sensing power-on of a memory system including a semiconductor memory device, determining whether to delay a garbage collection operation performed during an initial operation of the memory system, based on a sudden-power off (SPO) count value, and controlling the semiconductor memory device to perform the garbage collection operation based on the determination result.

Abstract: In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.

Abstract: As described herein, a system, method, and computer program are provided for batching a collection of elements in local memory for processing. A single collection of elements of data is stored in a local memory across a plurality of sub-collections. The single collection of elements is processed on a sub-collection basis, where each sub-collection is removed from the local memory upon completion of the processing of the elements in the sub-collection.

Abstract: A system for secured computing comprises: an interconnect; a processing element communicatively connected to the interconnect; and a memory controller communicatively connected to the interconnect and to a memory; wherein access of a memory block by the memory controller to and from the interconnect is accompanied by a security class of a plurality of security classes; wherein each memory block is associated with a security class assigned to the content stored in the memory block from amongst a plurality of security classes; wherein the associated security class of each memory block travels in the system together with the content of the associated memory block; wherein the memory controller employs at least one matrix; and wherein the at least one matrix defines interactions between the security classes of memory blocks of content as the content of the memory blocks which are being handled by at least the memory controller.