Abstract: There is provided a solid-state imaging device including: a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a second substrate including a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor that includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and a through electrode that is provided in the first substrate and the second substrate, and electrically couples the first substrate and the second substrate to each other and is partially in contact with the gate electrode.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A method of forming a semiconductor device includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. A push pin is extended through the first wafer chuck to distort the first wafer. A surface profile distortion of the first wafer is measured with a first surface profiler. A vacuum pressure of a vacuum zone on the first wafer chuck is adjusted using a measurement of the surface profile distortion. The first wafer chuck is moved towards the second wafer chuck so that the first wafer physically contacts the second wafer, and the first wafer is bonded to the second wafer.

Abstract: To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced.

Abstract: The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region.

Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a <100> crystallographic direction.

Abstract: A display device includes pixels; a first electrode and a second electrode disposed in each of the pixels, the first electrode and the second electrode being spaced apart from each other on a substrate; light-emitting elements disposed on the first electrode and the second electrode; a wavelength control layer disposed on the light-emitting elements; and a scattering layer disposed between the light-emitting elements and the wavelength control layer, the scattering layer comprising light-scattering particles, wherein the scattering layer is spaced apart from another scattering layer and is disposed in each of the pixels.

Abstract: Disclosed in the present specification are a micro LED display device in which an assembly electrode capable of forming a non-uniform electric field is assembled in a provided assembly hole, and a manufacturing method therefor.

Abstract: Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer having semiconductor devices formed in a plurality of respective areas demarcated thereon by a plurality of intersecting streets, a removing step of removing from the wafer a defective device region including a semiconductor device determined as a defective product among the semiconductor devices formed on the wafer, an enlarging step of enlarging a removed region formed in the wafer by removing the defective device region from the wafer, and an inlaying step of inlaying a device chip including a non-defective semiconductor device that is functionally identical to the semiconductor device determined as the defective product, in the enlarged removed region.

Abstract: Described herein is a technique capable of suppressing the generation of particles due to a film peeling in a process chamber. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate with an oxide film formed thereon into a process chamber wherein a metal-containing film is formed on a wall or other location in the process chamber; (b) supplying into the process chamber with at least one among: a gas containing a group 14 element and hydrogen; and a gas containing oxygen; and (c) forming the metal-containing film on the substrate after (b).

Abstract: An ultrasonic transducer device includes a patterned film stack disposed on first regions of a substrate, the patterned film stack including a metal electrode layer and a bottom cavity layer formed on the metal electrode layer. The ultrasonic transducer device further includes a planarized insulation layer disposed on second regions of the substrate layer, a cavity formed in a membrane support layer and a CMP stop layer, the CMP stop layer including a top layer of the patterned film stack and the membrane support layer formed over the patterned film stack and the planarized insulation layer. The ultrasonic transducer device also includes a membrane bonded to the membrane support layer. The CMP stop layer underlies portions of the membrane support layer but not the cavity.

Abstract: A color converting substrate includes: a base part having, defined therein a first light transmitting region, a second light transmitting region spaced apart from the first light transmitting region in a first direction, and a first light blocking region between the first light transmitting region and the second light transmitting region; a first color filter positioned on one surface of the base part and overlapping the first light transmitting region; a second color filter positioned on the one surface of the base part and overlapping the second light transmitting region; a light blocking pattern overlapping the first light blocking region and positioned on the one surface of the base part; and a light transmitting pattern positioned on the first color filter, the second color filter, and the light blocking pattern, wherein the first color filter and the second color filter include a coloring material of a first color.

Abstract: A display panel is provided. The display panel includes a display region, an insulating film, and a sealing film; the display region includes a pixel; and the pixel includes a display element and a color conversion layer. The insulating film covers the display element, the sealing film includes a region, the color conversion layer is sandwiched between the region and the insulating film, and the sealing film includes a region that is on the outside of the display region and in contact with the insulating film. The display element includes a first layer, a second layer, a third layer, and a fourth layer. The first layer contains a first material and a second material, the second layer contains a third material, the third layer contains a light-emitting material and a fourth material, the fourth layer contains a fifth material and a sixth material, the first material has a HOMO level higher than or equal to ?5.7 eV and lower than or equal to ?5.

Abstract: An anti-fuse unit includes: an anti-fuse device; a first selection transistor electrically connected with the anti-fuse device; and a second selection transistor electrically connected with the first selection transistor. Each of the anti-fuse device, the first selection transistor and the second selection transistor is provided with a gate oxide layer and a gate conductive layer, the gate oxide layer of the anti-fuse device, the gate oxide layer of the first selection transistor and the gate oxide layer of the second selection transistor have a same thickness, and the gate conductive layer of the anti-fuse device, the gate conductive layer of the first selection transistor and the gate conductive layer of the second selection transistor have a same thickness.

Abstract: Heat is efficiently discharged without impairing an imaging characteristic of a solid-state imaging element mounted on a substrate. A semiconductor device is provided with a substrate, the solid-state imaging element, and an adhesive portion that adheres the substrate and the solid-state imaging element. The substrate is a substrate provided with metal wiring. The solid-state imaging element is mounted on a surface of the substrate. The adhesive portion adheres a predetermined region on one surface of the solid-state imaging element to the substrate. The adhesive portion has predetermined thermal conductivity and discharges heat generated in the solid-state imaging element toward the substrate.

Abstract: Discussed is an assembly board including a base portion; a plurality of assembly electrodes extending in one direction and disposed on the base portion at predetermined intervals; a dielectric layer stacked on the base portion to cover the plurality of assembly electrodes; barrier ribs stacked on the dielectric layer and defining cells in which semiconductor light emitting diodes are seated at the predetermined intervals along an extending direction of the plurality of assembly electrodes so as to overlap a portion of the plurality of assembly electrodes; and a voltage applying unit connected to at least opposite ends of the plurality of assembly electrodes to apply one or more voltage signals to the plurality of assembly electrodes, wherein a voltage signal of the same polarity is applied to the plurality of assembly electrodes from the voltage applying unit connected to the opposite ends.

Abstract: There is method of processing a substrate comprising: (a) providing the substrate with a first base containing no oxygen, a second base containing oxygen, and a third base containing no oxygen and no nitrogen on its surface, wherein a protective film is formed on a surface of the third base; (b) modifying a surface of the second base to be fluorine-terminated by supplying a fluorine-containing gas to the substrate in a state where the protective film is formed on the surface of the third base; and (c) forming a film on a surface of the first base by supplying a film-forming gas to the substrate in a state where the surface of the second base is modified.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.