Abstract: Disclosed in the present specification are a micro LED display device in which an assembly electrode capable of forming a non-uniform electric field is assembled in a provided assembly hole, and a manufacturing method therefor.

Abstract: Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer having semiconductor devices formed in a plurality of respective areas demarcated thereon by a plurality of intersecting streets, a removing step of removing from the wafer a defective device region including a semiconductor device determined as a defective product among the semiconductor devices formed on the wafer, an enlarging step of enlarging a removed region formed in the wafer by removing the defective device region from the wafer, and an inlaying step of inlaying a device chip including a non-defective semiconductor device that is functionally identical to the semiconductor device determined as the defective product, in the enlarged removed region.

Abstract: Described herein is a technique capable of suppressing the generation of particles due to a film peeling in a process chamber. According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate with an oxide film formed thereon into a process chamber wherein a metal-containing film is formed on a wall or other location in the process chamber; (b) supplying into the process chamber with at least one among: a gas containing a group 14 element and hydrogen; and a gas containing oxygen; and (c) forming the metal-containing film on the substrate after (b).

Abstract: An ultrasonic transducer device includes a patterned film stack disposed on first regions of a substrate, the patterned film stack including a metal electrode layer and a bottom cavity layer formed on the metal electrode layer. The ultrasonic transducer device further includes a planarized insulation layer disposed on second regions of the substrate layer, a cavity formed in a membrane support layer and a CMP stop layer, the CMP stop layer including a top layer of the patterned film stack and the membrane support layer formed over the patterned film stack and the planarized insulation layer. The ultrasonic transducer device also includes a membrane bonded to the membrane support layer. The CMP stop layer underlies portions of the membrane support layer but not the cavity.

Abstract: A color converting substrate includes: a base part having, defined therein a first light transmitting region, a second light transmitting region spaced apart from the first light transmitting region in a first direction, and a first light blocking region between the first light transmitting region and the second light transmitting region; a first color filter positioned on one surface of the base part and overlapping the first light transmitting region; a second color filter positioned on the one surface of the base part and overlapping the second light transmitting region; a light blocking pattern overlapping the first light blocking region and positioned on the one surface of the base part; and a light transmitting pattern positioned on the first color filter, the second color filter, and the light blocking pattern, wherein the first color filter and the second color filter include a coloring material of a first color.

Abstract: A display panel is provided. The display panel includes a display region, an insulating film, and a sealing film; the display region includes a pixel; and the pixel includes a display element and a color conversion layer. The insulating film covers the display element, the sealing film includes a region, the color conversion layer is sandwiched between the region and the insulating film, and the sealing film includes a region that is on the outside of the display region and in contact with the insulating film. The display element includes a first layer, a second layer, a third layer, and a fourth layer. The first layer contains a first material and a second material, the second layer contains a third material, the third layer contains a light-emitting material and a fourth material, the fourth layer contains a fifth material and a sixth material, the first material has a HOMO level higher than or equal to ?5.7 eV and lower than or equal to ?5.

Abstract: An anti-fuse unit includes: an anti-fuse device; a first selection transistor electrically connected with the anti-fuse device; and a second selection transistor electrically connected with the first selection transistor. Each of the anti-fuse device, the first selection transistor and the second selection transistor is provided with a gate oxide layer and a gate conductive layer, the gate oxide layer of the anti-fuse device, the gate oxide layer of the first selection transistor and the gate oxide layer of the second selection transistor have a same thickness, and the gate conductive layer of the anti-fuse device, the gate conductive layer of the first selection transistor and the gate conductive layer of the second selection transistor have a same thickness.

Abstract: Heat is efficiently discharged without impairing an imaging characteristic of a solid-state imaging element mounted on a substrate. A semiconductor device is provided with a substrate, the solid-state imaging element, and an adhesive portion that adheres the substrate and the solid-state imaging element. The substrate is a substrate provided with metal wiring. The solid-state imaging element is mounted on a surface of the substrate. The adhesive portion adheres a predetermined region on one surface of the solid-state imaging element to the substrate. The adhesive portion has predetermined thermal conductivity and discharges heat generated in the solid-state imaging element toward the substrate.

Abstract: Discussed is an assembly board including a base portion; a plurality of assembly electrodes extending in one direction and disposed on the base portion at predetermined intervals; a dielectric layer stacked on the base portion to cover the plurality of assembly electrodes; barrier ribs stacked on the dielectric layer and defining cells in which semiconductor light emitting diodes are seated at the predetermined intervals along an extending direction of the plurality of assembly electrodes so as to overlap a portion of the plurality of assembly electrodes; and a voltage applying unit connected to at least opposite ends of the plurality of assembly electrodes to apply one or more voltage signals to the plurality of assembly electrodes, wherein a voltage signal of the same polarity is applied to the plurality of assembly electrodes from the voltage applying unit connected to the opposite ends.

Abstract: There is method of processing a substrate comprising: (a) providing the substrate with a first base containing no oxygen, a second base containing oxygen, and a third base containing no oxygen and no nitrogen on its surface, wherein a protective film is formed on a surface of the third base; (b) modifying a surface of the second base to be fluorine-terminated by supplying a fluorine-containing gas to the substrate in a state where the protective film is formed on the surface of the third base; and (c) forming a film on a surface of the first base by supplying a film-forming gas to the substrate in a state where the surface of the second base is modified.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

Abstract: An organic light emitting display device includes a substrate including a light emitting region, a first active layer having a source region and a drain region disposed in the light emitting region on the substrate, a gate insulation layer disposed on the first active layer, a first gate electrode disposed on the gate insulation layer, a first insulating interlayer disposed on the first gate electrode, a second insulating interlayer disposed on the first insulating interlayer, a first source electrode disposed on the second insulating interlayer, the first source electrode being connected to the source region of the first active layer through a contact hole formed in the gate insulation layer, the first insulating interlayer, and the second insulating interlayer, a protective insulating layer disposed on the first source electrode, a first drain electrode disposed on the protective insulating layer, the first drain electrode being connected to the drain region of the first active layer through a contact hole

Abstract: An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

Abstract: A microelectromechanical system (MEMS) test structure includes a plurality of capacitors formed from sense electrodes and capacitive plates having a predetermined geometry and size associated with a related MEMS device such as a MEMS sensor. Based on the predetermined relationships between the capacitors of the test structure, and between the test structure and the MEMS devices, an effect of fringing fields on the sensed capacitances of the MEMS devices may be eliminated, and the capacitive gap of the MEMS device may be accurately measured.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

Abstract: Disclosed are apparatuses and methods for providing a substrate onto a substrate support in a processing chamber, generating an inert plasma in the processing chamber, and maintaining the inert plasma to heat the substrate to a steady state temperature, suitable for conducting plasma-enhanced chemical vapor deposition (PECVD), in less than 30 seconds from providing the substrate onto the substrate support. An apparatus may include a processing chamber, a process station that includes a substrate support, a process gas unit configured to flow an inert gas onto a substrate supported by the substrate support, a plasma source configured to generate an inert plasma in the process station, and a controller with instructions configured to flow the inert gas onto the substrate, generate the inert plasma in the first process station, and maintain the inert plasma to thereby heat the substrate.

Abstract: An electronic device is disclosed. The electronic device comprises: a transfer device capable of moving, to a target substrate, a plurality of LEDs arranged in a transfer substrate, and arranging same; a storage unit in which feature information of each of the plurality of LEDs is stored; and a processor for controlling the transfer device such that each of a plurality of LEDs is arranged in an arrangement location on the target substrate of each of a plurality of LEDs on the basis of the stored feature information.

Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.