Patents Examined by Yasser A. Abdelaziez
  • Patent number: 10535809
    Abstract: In a general aspect, an integrated microwave circuit is disclosed for processing quantum information. The integrated microwave circuit includes a substrate having a first surface and a second surface opposite the first surface. The substrate is formed of a silicon oxide material having a loss tangent no greater than 1×10?5 at cryogenic temperatures at or below 120 K. The integrated microwave circuit also includes qubit circuitry disposed on the first surface that includes a Josephson junction. A ground plane is disposed on the first surface or the second surface. In some variations, the silicon oxide material is fused silica. In other variations, the silicon oxide material is crystalline quartz.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 14, 2020
    Assignee: Rigetti & Co, Inc.
    Inventor: Nagesh Vodrahalli
  • Patent number: 10535522
    Abstract: Provided herein are techniques for treating vertical surface features of a semiconductor device with ions. In some embodiments, a method for forming a semiconductor device, may include providing a set of surface features extending from a substrate, the set of surface features including a sidewall. The method may include treating the sidewall with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the substrate. The method may further include rotating the substrate about the perpendicular to the plane while the sidewall is treated with the ion beam to impact an entire height of the sidewall with the ion beam.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 14, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Gang Shu, Glen Gilchrist, Shurong Liang
  • Patent number: 10529572
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Patent number: 10527933
    Abstract: A wire grid polarizer includes a base substrate, a wire grid pattern, a first stitch line extending in a first direction, and a second stitch line extending in a second direction which crosses the first direction, and including a first portion and a second portion which are discontinuous from each other, in which the wire grid pattern is evenly formed on all of the base substrate except where the first and second stitch lines exist, and the first and second stitch lines are where the wire grid pattern is unevenly formed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Won Park, Taewoo Kim, Lei Xie, Daehwan Jang, Dae-Young Lee, Gugrae Jo
  • Patent number: 10527654
    Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 7, 2020
    Assignee: Vishay SIliconix, LLC
    Inventors: M. Ayman Shibib, Wenjie Zhang
  • Patent number: 10516064
    Abstract: A technique relates to a semiconductor device. A first stack includes a first plurality of nanowires respectively coupled to first source and drain regions, and a second stack includes a second plurality of nanowires respectively coupled to second source and drain regions. First source and drain contacts couple to a first predefined number of the first plurality of nanowires. Second source and drain contacts to couple to a second predefined number of the second plurality of nanowires, wherein the first predefined number is different from the second predefined number.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang
  • Patent number: 10516033
    Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Yu, Sheng-chen Wang, Sai-Hooi Yeong
  • Patent number: 10509394
    Abstract: Techniques to facilitate visualization of an application associated with an industrial automation environment are disclosed. In at least one implementation, a display composer interface is presented that enables a user to design a customized display layout for the application associated with the industrial automation environment. Data display instructions are received comprising a user selection of at least one data item associated with an operation of a machine in the industrial automation environment. Position information that identifies where to display the at least one data item is also received. The data display instructions and the position information are processed to generate the customized display layout for the application. Based on the customized display layout, a graphical user interface is rendered to the application having the at least one data item positioned according to the position information.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 17, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Ashish Anand, Vojtech Sipek, Scott N. Sandler, Zdenek Kodejs, Damon Purvis
  • Patent number: 10510742
    Abstract: An IC structure includes a substrate, a deep n-well (DNW), a first device, a second device, a first electrical path and a second electrical path. The DNW is in the substrate. The first device is formed inside the DNW and connected to a first lower reference voltage and a first higher reference voltage. The second device is formed in the substrate and outside the DNW, and connected to a second lower reference voltage and a second higher reference voltage. The first electrical path is electrically connected between the first device and the second device. The second electrical path is electrically connected between the first lower reference voltage and the second lower reference voltage. A second metal layer that includes the second electrical path is located in an area outside of an area above a first metal layer in which the first electrical path is located.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lin Chu, Hsi-Yu Kuo
  • Patent number: 10508027
    Abstract: The present disclosure provides a CMOS structure, including a substrate, a metallization layer over the substrate, a sensing structure over the metallization layer, and a signal transmitting structure adjacent to the sensing structure. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier over the outgassing layer; and an electrode over the patterned outgassing barrier. The signal transmitting structure electrically couples the electrode and the metallization layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jung-Huei Peng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Patent number: 10510971
    Abstract: Described are materials and methods for fabricating low-voltage MHz ion-gel-gated thin film transistor devices using patternable defect-free ionic liquid gels. Ionic liquid gels made by the initiated chemical vapor deposition methods described herein exhibit a capacitance of about 1 ?F cm?2 at about 1 MHz, and can be as thin as about 20 nm to about 400 nm.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: December 17, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Andong Liu, Karen K. Gleason, Minghui Wang
  • Patent number: 10504872
    Abstract: A method of batch transferring micro semiconductor structures is provided for effectively and efficiently picking up a batch of or a large amount of micro structures and transferring them to a target substrate, so it can be widely applied in transferring a lot of various micro semiconductor structures. The method includes steps of: attaching an adhesive material to a plurality of array-type micro semiconductor structures; and providing a roll-to-attach mechanism for alternately processing linear contacts between the array-type micro semiconductor structures and a target substrate. The array-type micro semiconductor structures are optionally picked up in batch from the adhesive material and transferred in batch to the target substrate as the linear contacts are alternately processed.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: December 10, 2019
    Assignee: ULTRA DISPLAY TECHNOLOGY CORP.
    Inventor: Hsien-Te Chen
  • Patent number: 10505005
    Abstract: Techniques for reducing the specific contact resistance of metal—semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 10, 2019
    Assignee: ACORN SEMI, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 10496051
    Abstract: An event analyzing device includes an event collector configured to collect log data of a manual operation event performed by an operator of a plant, an event analyzer configured to analyze a manual operation method or a manual operation intention of the manual operation event based on the log data, a manual operation sequence extractor configured to extract the manual operation method or the manual operation intention for each predetermined period as manual operation sequences in order of time, a manual operation sequence classifier configured to classify the manual operation sequences in which manual operations are in a similar order from among the manual operation sequences, a manual operation procedure constructor configured to construct a manual operation procedure of the operator based on the manual operation sequences, a process data collector configured to collect process data of the plant, and a manual operation condition estimator configured to estimate an execution condition under which manual oper
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: December 3, 2019
    Assignee: Yokogawa Electric Corporation
    Inventors: Zhuo Liu, Yuichi Sakuraba
  • Patent number: 10497804
    Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Park, Beom-Jin Park, Yun-Il Lee, Jung-Gun You, Dong-Hun Lee
  • Patent number: 10490510
    Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 26, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Dipak Sengupta
  • Patent number: 10490642
    Abstract: A semiconductor device includes a semiconductor substrate having a first side, and a trench structure having a bottom and a sidewall. The bottom has at least first and second bottom portions laterally adjacent to one another. Each bottom portion has a concave shape with a ridge formed between the first and second bottom portions. An insulating material covers the sidewall and first bottom portion of the trench structure while leaving the second bottom portion uncovered. A mesa region extends to the first side of the substrate and forms the sidewall of the trench structure. The device also includes a first silicide layer on a top region of the mesa region, a second silicide layer on the second bottom portion of the trench structure, a first metal layer on and in contact with the first silicide layer, and a second metal layer on and in contact with the second silicide layer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Dresden GmbH & Co. KG
    Inventors: Rolf Weis, Martin Bartels, Marko Lemke, Stefan Tegen
  • Patent number: 10481628
    Abstract: Power consumption is sensed for individual subsystems of an agricultural machine. Visual indicia are generated, that are indicative of the sensed power consumption, for each individual subsystem. A user interface mechanism is controlled to display the visual indicia, indicating power consumption of the individual subsystems on the harvesting machine.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 19, 2019
    Assignee: Deere & Company
    Inventor: William D. French, Jr.
  • Patent number: 10480315
    Abstract: Systems and methods for calculating reservoir characteristics, including well pressure and flow rates are disclosed. Plotting and monitoring a plot of pressure (p) and flow rate (q) as p/q on a y-axis and 1/q on an x-axis can provide insight into well characteristics with zero RMS error.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: November 19, 2019
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Varma Gottumukkala, Bobby Dale Poe, Jr.
  • Patent number: 10475913
    Abstract: The present invention provides an epitaxial structure of N-face AlGaN/GaN, its active device, and the method for fabricating the same. The structure comprises a substrate, a C-doped buffer layer on the substrate, a C-doped i-GaN layer on the C-doped buffer layer, a i-AlyGaN buffer layer on the C-doped i-GaN layer, an i-GaN channel layer on the C-doped i-AlyGaN buffer layer, and an i-AlxGaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of N-face AlGaN/GaN below the p-GaN inverted trapezoidal gate structure will be depleted. Then the 2DEG is located at the junction between the i-GaN channel layer and the i-AlyGaN layer, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs).
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 12, 2019
    Inventor: Chih-Shu Huang