Patents Examined by Yasser A. Abdelaziez
  • Patent number: 11834328
    Abstract: A semiconductor package with design features, including an isolation structure for internal components and a flexible electrical connection, that minimizes errors due to environmental temperature, shock, and vibration effects. The semiconductor package may include a base having a first portion surrounded by a second portion. A connector assembly may be attached to the first portion. The connector assembly may extend through an opening in the base. A lid attached may be attached to, at least, the second portion. The attached lid may form a hermetically-sealed cavity defined by an upper surface of the first portion, the connector assembly, and an inner surface of the lid. An elastomer pad may be on the first portion and a sub-assembly may be on the elastomer pad. A flexible electrical connection may be formed between the connector assembly and the sub-assembly.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 5, 2023
    Assignee: InvenSense, Inc.
    Inventors: Hamid Eslampour, Karthik Katingari, Adam Martin
  • Patent number: 11832490
    Abstract: An electronic device includes a first electronic unit and a second electronic unit. The first electronic unit emits a blue light having a first spectrum, the first spectrum has a first intensity, and the first intensity is a maximum intensity of the first spectrum. The second electronic unit emits a light having a second spectrum different from the first spectrum, the second spectrum has a second intensity in a range from 300 nm to 460 nm, and the second intensity is a maximum intensity in the range from 300 nm to 460 nm of the second spectrum. The first intensity is greater than the second intensity.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: November 28, 2023
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai
  • Patent number: 11827513
    Abstract: A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuei-Sung Chang, Tai-Bang An, Chun-Wen Cheng, Hung-Hua Lin
  • Patent number: 11817456
    Abstract: Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: November 14, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guillaume Alexandre Blin, Ambarish Roy, Seungwoo Jung
  • Patent number: 11804533
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 31, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11804561
    Abstract: A light receiving element (1) according to an embodiment of the present disclosure includes: a semiconductor layer including a compound semiconductor material; a first impurity diffusion region (12A) provided on one surface of the semiconductor layer; and a second impurity diffusion region (12B) provided around the first impurity diffusion region (12A). The second impurity diffusion region (12B) has a lower impurity concentration than an impurity concentration of the first impurity diffusion region (12A).
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: October 31, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Shuji Manda
  • Patent number: 11798987
    Abstract: The present invention is related to a substrate (10) for a controlled implantation of ions (80) into a bulk (20), the substrate (10) comprising the bulk (20) composed of a crystalline first material (70), the bulk (20) comprising an implantation region (28) and a surface (22), wherein the implantation region (28) is located within the bulk (20) and along an implantation direction (82) at an implantation depth (26) below an implantation area (24) on the surface (10) of the bulk (20).
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 24, 2023
    Assignee: PARCAN NANOTECH CO., LTD.
    Inventors: Ivo Rangelow, Xiang-Qian Zhou, Dimitre Karpuzov
  • Patent number: 11799396
    Abstract: A method for manufacturing an electromechanical actuator includes providing a primary stack of layers comprising a monocrystalline layer, providing a secondary stack of layers, and forming, in the etching layer, at least three pads. The method further includes encapsulating the three pads by a first encapsulation layer, assembling the primary stack of layers with the secondary stack of layers, removing the first substrate, and forming a movable electrode in the monocrystalline layer.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 24, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Louis Hutin, Giulia Usai
  • Patent number: 11791280
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hua Tai, Pai-Chou Liu, Yun-Chih Fei, Wen-Pin Huang, Sheng-Hong Zheng
  • Patent number: 11784237
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 10, 2023
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Kingyuen Wong, Han-Chin Chiu, Ming-Hong Chang, Chunhua Zhou, Jinhan Zhang
  • Patent number: 11764290
    Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a <100> crystallographic direction.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis
  • Patent number: 11764137
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: September 19, 2023
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Cheng Yuan Chen
  • Patent number: 11760627
    Abstract: A microelectromechanical system (MEMS) sensor package includes a laminate that provides physical support and electrical connection to a MEMS sensor. A resin layer is embedded within an opening of the laminate and a MEMS support layer is embedded within the opening by the resin layer. A MEMS structure of the MEMS sensor is located on the upper surface of the MEMS support layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 19, 2023
    Assignee: InvenSense, Inc.
    Inventors: Roberto Brioschi, Benyamin Gholami Bazehhour, Milena Vujosevic, Kazunori Hayata
  • Patent number: 11749742
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsungyu Hung, Pang-Yen Tsai, Pei-Wei Lee
  • Patent number: 11746000
    Abstract: A MEMS device includes a membrane portion, a piezoelectric layer made of a piezoelectric single crystal, a first electrode on a first surface of the piezoelectric layer, a second electrode on a second surface of the piezoelectric layer opposite to the first direction, and a first layer covering the first surface of the piezoelectric layer. At least a portion of the piezoelectric layer is included in the membrane portion. Each of the first electrode and the second electrode has a tapered cross-sectional shape with a width which decreases with increasing distance from the piezoelectric layer on a cross section along a plane vertical to the surface in the first direction.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 5, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Kishimoto, Shinsuke Ikeuchi, Katsumi Fujimoto, Tetsuya Kimura, Fumiya Kurokawa
  • Patent number: 11742248
    Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 11738993
    Abstract: A silicon substrate having a first silicon substrate having a first surface with a cavity and a second surface opposite the first surface; a first silicon oxide film having a thickness d1 on the first surface; a second silicon oxide film having a thickness d2 on a bottom of the cavity; and a third silicon oxide film having a thickness d3 on the second surface, where d1?d3 and d1<d2, or d3<d1 and d2<d1.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: August 29, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yutaka Kishimoto
  • Patent number: 11737378
    Abstract: A graphene/doped 2D layered material Van der Waals heterojunction superconducting composite structure, a superconducting device and a manufacturing method therefor, which relate to the technical field of superconducting materials. Said structure includes: a (2n+1)-layered structure formed by graphene layers and doped 2D layered materials which are alternately provided. An outer layer of the layered structure is the graphene layer, n is an integer between 1 to 50, a superconducting region is formed by a region in which the graphene perpendicularly overlaps the doped 2D layered material, and the graphene layers and the doped two-dimensional layered materials are self-assembled into one piece by means of a Van der Waals force.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 22, 2023
    Inventor: Xuyang Sun
  • Patent number: 11735426
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Patent number: 11731871
    Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 22, 2023
    Assignee: InvenSense, Inc.
    Inventors: Ashfaque Uddin, Daesung Lee, Alan Cuthbertson