Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.

Abstract: Nano-electromechanical systems (NEMS) sensor devices that utilize thin electrically conductive membranes, which can be, for example, graphene membranes. The NEMS devices can have a trough shape (such as a serpentine shape arrangement) of the electrically conductive membrane. The thin, electrically conductive membrane has membrane-structures disposed upon it in an array of cavities. These membrane structures are between the thin, electrically conductive membrane and the main membrane trace. Such an arrangement increases the sensitivity of the NEMS sensor device. The electrically conductive membrane can be controllably wicked down on the edge of the oxide cavity to increase the sensitivity of the NEMS sensor device. Such NEMS sensor devices include NEMS sensor devices that are well suited to applications that measure magnetic fields that, operate below 10 kHz, such as brain-computer interfaces.

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.

Abstract: A semiconductor device in which a variation of transistor characteristics is small is provided. The semiconductor device includes a transistor. The transistor includes a first insulator, a first oxide over the first insulator, a first conductor, a second conductor, and a second oxide, which is positioned between the first conductor and the second conductor, over the first oxide, a second insulator over the second oxide, and a third conductor over the second insulator. A top surface of the first oxide in a region overlapping with the third conductor is at a lower position than a position of a top surface of the first oxide in a region overlapping with the first conductor. The first oxide in the region overlapping with the third conductor has a curved surface between a side surface and the top surface of the first oxide, and the curvature radius of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

Abstract: A display screen allowing higher pixel density and thus better screen resolution by virtue of the structures connecting to LED chip light sources includes a substrate, a number of pad structures, the LED chips, and a number of carrier boards. Each pad structure includes a positive electrode pad and three negative electrode pads. Each LED chip package includes a red light chip, a green light chip, and a blue light chip arranged on the three negative electrode pads. Each carrier board includes a positive electrode connection terminal and a negative electrode connection terminal, the positive electrode connection terminal is electrically connected to the positive electrode pad, the negative electrode connection terminal is electrically connected to one red light chip, one green light chip, or one blue light chip. The disclosure also provides a displaying device having the display screen.

Abstract: A display device and a spliced display panel are provided. The spliced display panel has: a display assembly, where the display assembly includes a display substrate and first connection terminals electrically connected to the display substrate; a driving backplane, where the display assembly is arranged on the driving backplane; the driving backplane includes a communication circuit layer located in the display area, the communication circuit layer includes second connection terminals bound to the first connection terminals; and a driving integrated circuit electrically connected to the second connection terminals.

Abstract: A semiconductor device includes an IGBT region in which an IGBT element is formed and an FWD region in which an FWD element is formed. The IGBT region includes a first region and a second region different from the first region. The FWD region and the first region of the IGBT region have a carrier extraction portion that facilitates extraction of carriers injected from a second electrode compared to the second region when a forward bias for causing the FWD element to operate as a diode is applied between a first electrode and the second electrode.

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

Abstract: There is provided a solid-state imaging device including: a first substrate including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a second substrate including a semiconductor layer and a pixel transistor, the semiconductor layer being stacked on the first substrate, and the pixel transistor that includes a gate electrode opposed to the semiconductor layer, and reads the signal electric charge of the electric charge accumulation section; and a through electrode that is provided in the first substrate and the second substrate, and electrically couples the first substrate and the second substrate to each other and is partially in contact with the gate electrode.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A method of forming a semiconductor device includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. A push pin is extended through the first wafer chuck to distort the first wafer. A surface profile distortion of the first wafer is measured with a first surface profiler. A vacuum pressure of a vacuum zone on the first wafer chuck is adjusted using a measurement of the surface profile distortion. The first wafer chuck is moved towards the second wafer chuck so that the first wafer physically contacts the second wafer, and the first wafer is bonded to the second wafer.

Abstract: To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced.

Abstract: The present disclosure provides an integrated circuit structure of a group III nitride semiconductor, a manufacturing method thereof, and use thereof. The integrated circuit structure is a complementary circuit of HEMT and HHMT based on the group III nitride semiconductor, and can realize the integration of HEMT and HHMT on the same substrate, and the HEMT and the HHMT respectively have a polarized junction with a vertical interface, the crystal orientations of the polarized junctions of the HEMT and the HHMT are different, the two-dimensional carrier gas forms a carrier channel in a direction parallel to the polarized junction, and corresponding channel carriers are almost depleted by burying the doped region.

Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a <100> crystallographic direction.

Abstract: A display device includes pixels; a first electrode and a second electrode disposed in each of the pixels, the first electrode and the second electrode being spaced apart from each other on a substrate; light-emitting elements disposed on the first electrode and the second electrode; a wavelength control layer disposed on the light-emitting elements; and a scattering layer disposed between the light-emitting elements and the wavelength control layer, the scattering layer comprising light-scattering particles, wherein the scattering layer is spaced apart from another scattering layer and is disposed in each of the pixels.

Abstract: Disclosed in the present specification are a micro LED display device in which an assembly electrode capable of forming a non-uniform electric field is assembled in a provided assembly hole, and a manufacturing method therefor.

Abstract: Disclosed herein is an integrated component formed by a first wafer having first and second trenches defined in a top surface thereof, and a second wafer coupled to the first wafer and formed by a substrate with a structural layer thereon that integrated an electromagnetic radiation detector overlying the second trench. A first cap is coupled to the second wafer, overlies the electromagnetic radiation detector, and serves to define a first air-tight chamber in which the electromagnetic radiation detector is positioned. A stator, a rotor, and a mobile mass are integrated within the substrate and form a drive assembly for driving the mobile mass. The rotor overlies the first trench. A second cap is coupled to the second wafer, overlies the mobile mass, and serving to define a second air-tight chamber in which the mobile mass is positioned.