Patents Examined by Yasser A. Abdelaziez
  • Patent number: 11669710
    Abstract: Processing raw data stored in an historian device for determining an amount of products passed through a process element in a process control environment is described. A count value is incremented by a counter at a rate at which products pass through the process element. The count value rolls over to zero when the count value reaches a rollover value R. An historian device periodically receives count value data points from the counter. A deadband value D is set in the historian device for distinguishing between rollovers, resets, and reversals. A client device queries the historian device for an amount of products passed through the process element for a timeframe. The historian device selects a set of count value data points from within the queried timeframe. The historian device determines, based on the selected data points and their quality, an amount of products passed through the process element.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: June 6, 2023
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Vinay T. Kamath, Yevgeny Naryzhny, Alexander Vasilyevich Bolotskikh, Abhijit Manushree, Elliott Middleton, Bala Kamesh Sista
  • Patent number: 11661335
    Abstract: A method for fabricating a cantilever having a device surface, a tapered surface, and an end region includes providing a semiconductor substrate having a first side and a second side opposite to the first side and etching a predetermined portion of the second side to form a plurality of recesses in the second side. Each of the plurality of recesses comprises an etch termination surface. The method also includes anisotropically etching the etch termination surface to form the tapered surface of the cantilever and etching a predetermined portion of the device surface to release the end region of the cantilever.
    Type: Grant
    Filed: May 22, 2021
    Date of Patent: May 30, 2023
    Assignee: Magic Leap, Inc.
    Inventors: Steven Alexander-Boyd Hickman, Sarah Colline McQuaide, Abhijith Rajiv, Brian T. Schowengerdt, Charles David Melville
  • Patent number: 11661333
    Abstract: A semiconductor structure includes a substrate; a sensing device disposed over the substrate and including a plurality of protruding members protruded from the sensing device; a sensing structure disposed adjacent to the sensing device and including a plurality of sensing electrodes protruded from the sensing structure towards the sensing device; and an actuating structure disposed adjacent to the sensing device and configured to provide an electrostatic force on the sensing device based on a feedback from the sensing structure. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Jhih Mao, Shang-Ying Tsai, Kuei-Sung Chang, Chun-Wen Cheng
  • Patent number: 11655138
    Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Cheng Hsu, Kuo-Hao Lee, Jui-Chun Weng, Ching-Hsiang Hu, Ji-Hong Chiang, Lavanya Sanagavarapu, Chia-Yu Lin, Chia-Chun Hung, Jia-Syuan Li, Yu-Pei Chiang
  • Patent number: 11655146
    Abstract: A preclean process may be omitted from a eutectic bonding sequence. To remove oxide from one or more surfaces of a device wafer of a micro-electromechanical-system (MEMS) structure, a duration of an acid-based etch process in the eutectic bonding sequence may be increased relative to the duration of the acid-based etch process when the preclean process is performed. The increased duration of the acid-based etch process enables the acid-based etch process to remove the oxide from the one or more surfaces of the device wafer without the use of a preceding preclean process. This reduces the complexity and cycle time of the eutectic bonding sequence, reduces the risk of stiction between suspended mechanical components of the MEMS structure, and/or reduces the likelihood that the MEMS structure may be rendered defective or inoperable during manufacturing, which increases process yield.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: May 23, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Ta Kuo, I-Shi Wang, Tzu-Ping Yang, Hsing-Yu Wang, Shu-Han Chao, Hsi-Cheng Hsu, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Patent number: 11655145
    Abstract: The present disclosure relates to a MEMS vibrator or the like that has excellent chemical resistance and an excellent mechanical strength and that is easily thinned. The present disclosure is a MEMS vibrator comprising: a vibrating film including a graphite film; and a silicon member supporting the vibrating film, the graphite film having a thickness of 50 nm or more and less than 20 ?m, and the graphite film having a Young's modulus along a graphite film plane direction of 700 GPa or more.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 23, 2023
    Assignee: KANEKA CORPORATION
    Inventors: Junji Sone, Mutsuaki Murakami
  • Patent number: 11651978
    Abstract: A protective sheet application method for applying a protective sheet on a front surface of a substrate includes mounting the substrate on a support table in a vacuum chamber, mounting the protective sheet on the substrate to separate a space in the vacuum chamber into a first compartment and a second compartment, depressurizing the first compartment to a predetermined air pressure and also depressurizing the second compartment, opening the depressurized second compartment to the atmosphere to bring the protective sheet into close contact with the substrate by a predetermined force, and opening the depressurized first compartment to the atmosphere to separate the lower housing and the upper housing from each other. A protective sheet application apparatus for applying the protective sheet on the front surface of the substrate includes the vacuum chamber.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 16, 2023
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 11646199
    Abstract: Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 9, 2023
    Assignees: International Business Machines Corporation, ULVAC. Inc.
    Inventors: John Rozen, Martin Michael Frank, Yohei Ogawa
  • Patent number: 11644757
    Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Changhua Liu, Jianyong Mo, Liang Zhang
  • Patent number: 11637179
    Abstract: Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 25, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chanro Park, Juntao Li, Ruilong Xie
  • Patent number: 11634320
    Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Jung Chen, Shih-Wei Lin
  • Patent number: 11621404
    Abstract: A display device has a first electrode provided corresponding to each of a plurality of pixels in a region in which the plurality of pixels is provided, a second electrode provided over the plurality of pixels and extending to a contact region provided outside the pixel region, a light emitting layer provided between the first electrode and the second electrode, a third electrode provided in the contact region, an organic insulating layer covering the third electrode and provided with a contact hole exposing the third electrode, and a connection portion between the second electrode and the third electrode in the contact hole, wherein the maximum distance between any two points on the outer periphery of the connection portion is 1 ?m or more and 100 ?m or less.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 4, 2023
    Assignee: Japan Display Inc.
    Inventors: Mitsuhide Miyamoto, Hajime Akimoto, Yuko Matsumoto, Yusuke Tada
  • Patent number: 11610912
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 21, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Hidenobu Nagashima
  • Patent number: 11610945
    Abstract: An electronic device includes a first electronic unit and a second electronic unit. The first electronic unit includes a first light conversion layer and emits a blue light having a first spectrum. The first spectrum has a first intensity, and the first intensity is a maximum intensity of the first spectrum. The second electronic unit emits a light having a second spectrum different from the first spectrum, and the second spectrum has a second intensity in a range from 300 nm to 460 nm, and the second intensity is a maximum intensity in the range from 300 nm to 460 nm of the second spectrum. A ratio of the second intensity to the first intensity is in a range from 0.06% to 10.0%.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: March 21, 2023
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai
  • Patent number: 11610883
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: March 21, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Kazuhito Nakai, Yusuke Tanaka
  • Patent number: 11610974
    Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 21, 2023
    Assignee: Acorn Semi, LLC
    Inventors: Walter A. Harrison, Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 11603311
    Abstract: A MEMS switch is actuatable by a fluid, and includes a piezoelectric pressure sensor that detects the movement of a fluid generating a negative pressure. The piezoelectric pressure sensor is formed by a chip of semiconductor material having a through cavity and a sensitive membrane, which extends over the through cavity and has a first and a second surface. The piezoelectric pressure sensor is mounted on a face of a board having a through hole so that the through cavity overlies and is in fluid connection with the through hole. The board has a fixing structure, which enables securing in an opening of a partition wall separating a first and a second space from each other. The board is arranged so that the first surface of the sensitive membrane faces the first space, and the second surface of the sensitive membrane faces the second space.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: March 14, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Enri Duqi, Fabrizio Cerini, Lorenzo Baldo
  • Patent number: 11600488
    Abstract: There is provided a technique that includes: loading an m-th substrate into a process chamber, wherein m is an integer less than n; forming a film on the m-th substrate by heating the m-th substrate in the process chamber; unloading the m-th substrate from the process chamber; waiting for a predetermined time in the process chamber, in a state where the substrates are not present in the process chamber, after the act of unloading; loading a next substrate, which is one of the n substrates to be processed next, into the process chamber, after the act of waiting; and forming a film on the next substrate by heating the next substrate in the process chamber.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 7, 2023
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Naofumi Ohashi, Toshiyuki Kikuchi
  • Patent number: 11591210
    Abstract: A transducer assembly can include a base. The transducer assembly can include a stress isolation standoff located on the base. The transducer assembly can include a MEMS die disposed on the stress isolation standoff. The transducer assembly can include a die attach adhesive disposed between the MEMS die and the base. The die attach adhesive can bond the MEMS die to the base. The stress isolation standoff can be embedded in the die attach adhesive between the base and the MEMS die.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: February 28, 2023
    Assignee: Knowles Electronics, LLC
    Inventor: Timothy Pachla
  • Patent number: 11584639
    Abstract: A method of manufacturing a plurality of resonators, each formed by a membrane sealing a cavity, includes forming a plurality of cavities starting from one face called the front face of a support substrate, the plurality of cavities comprising central cavities and peripheral cavities arranged around the assembly formed by the central cavities, and forming central membranes and peripheral membranes covering the central cavities and peripheral cavities, respectively, by the transfer of a coverage film on the front face of the support substrate. At least part of the peripheral membranes is removed.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 21, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruno Fain, Caroline Coutier