Abstract: A method of providing a MEMS device including a through-hole in a layer of structural material using a multitude of MEMS method steps. A versatile method to create a through-hole, in particular a multitude thereof, involves a step of exposing a polymeric layer of positive photoresist in a direction from the outer surface of the positive photoresist to light resulting in an exposed layer of positive photoresist including relatively strongly depolymerized positive photoresist in the top section of a recess while leaving relatively less strongly depolymerized positive photoresist in the bottom section of the recess.

Abstract: A deposition method includes forming a nitride film on a surface of a substrate; and performing, after the depositing, plasma purging supplying a noble gas activated as a plasma. The forming of the nitride film includes a) forming adsorption inhibitors on the surface of the substrate, by supplying a chlorine gas activated by a plasma and by causing the activated chlorine gas to be adsorbed on the surface of the substrate; b) causing a raw material gas, containing silicon and chlorine or a metal and chlorine, to be adsorbed on a region in the surface of the substrate on which the adsorption inhibitors are not present, by supplying the raw material gas on the surface of the substrate; and c) depositing the nitride film on the surface of the substrate, by supplying a nitriding gas to cause the raw material gas to be reacted with the nitriding gas.

Abstract: Disclosed a MEMS assembly and a manufacturing method thereof. The manufacturing method comprises: forming a groove on a sensor chip; forming a bonding pad on a circuit chip; bonding the sensor chip and the circuit chip together to form a bonding assembly; performing a first dicing process at a first position of the sensor chip to penetrate through the sensor chip to the groove; performing a second dicing process at a second position of the sensor chip to penetrate through the sensor chip and the circuit chip, for obtaining an individual MEMS assembly by singulating the bonding assembly, wherein location of the groove corresponds to a position of the bonding pad, and an opening is formed in the sensor chip to expose the bonding pad when the second dicing process is performed. The method uses two dicing process respectively achieving different depths to expose the bonding pad of the sensor chip and singulate the MEMS assembly, respectively, to improve yield and reliability.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a metallization layer over the substrate, and a sensing structure over the metallization layer. The sensing structure includes an outgassing layer over the metallization layer, a patterned outgassing barrier in proximity to a top surface of the outgassing layer, the patterned outgassing barrier exposing a portion of the outgassing layer, and an electrode over the patterned outgassing barrier. The method for manufacturing the semiconductor device is also provided.

Abstract: A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.

Abstract: In a microelectromechanical component according to the invention, at least one microelectromechanical element (5), electrical contacting elements (3) and an insulation layer (2.2) and thereon a sacrificial layer (2.1) formed with silicon dioxide are formed on a surface of a CMOS circuit substrate (1) and the microelectromechanical element (5) is arranged freely movably in at least a degree of freedom. At the outer edge of the microelectromechanical component, extending radially around all the elements of the CMOS circuit, a gas- and/or fluid-tight closed layer (4) which is resistant to hydrofluoric acid and is formed with silicon, germanium or aluminum oxide is formed on the surface of the CMOS circuit substrate (1).

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

Abstract: A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.

Abstract: A micromechanical apparatus and a corresponding production method are described. The micromechanical apparatus encompasses a base substrate having a front side and a rear side; and a cap substrate, at least one surrounding trench having non-flat side walls being embodied in the front side of the base substrate; the front side of the base substrate and the trench being coated with at least one metal layer; the non-flat side walls of the trench being covered nonconformingly with the metal so that they do not form an electrical current path in a direction extending perpendicularly to the front side; and a closure, in particular a seal-glass closure, being embodied in the region of the trench between the base substrate and the cap substrate.

Abstract: Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand.

Abstract: An integrated package method for MEMS element and ASIC chip includes forming a re-layout layer on a front surface of an ASIC wafer; coating an organic compound layer on the re-layout layer and applying a lithography process to the organic compound layer to from a microcavity array; aligning and bonding an electrode connection pad layer on a front surface of an MEMS element with the microcavity array to form a closed cavity structure; thinning and exposing a silicon substrate on a back surface of the MEMS element to a desired thickness; applying the lithographic process on the MEMS element to expose the electrode connection pad layer and an electrical contact area of the re-layout layer; and manufacturing a metal connection member connected to the electrode connection pad layer and the electrical contact area. An integrated package structure for MEMS element and ASIC chip is also provided.

Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

Abstract: A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

Abstract: A method and system of a predictive maintenance IoT system comprises receiving a plurality of sensor data over a communications network and determining one or more clusters from the sensor data based on a pre-determined rule set. Further, the sensor data is classified through a machine learning engine and the sensor data is further base-lined through a combination of database architecture, data training architecture, and a base-lining algorithm. Intensity or degree of fault state is mapped to a fuel gauge to be depicted on a user interface and a predictive maintenance state is predicted through a regression model and appropriate alarm is raised for user action.

Abstract: Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H2 and/or NH3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.

Abstract: Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.

Abstract: An organic EL display device is provided with an eaves body that includes a protruding portion outside a display region on a TFT substrate, along an edge portion on which a first inorganic layer and a second inorganic layer of a sealing film are provided. The first inorganic layer and the second inorganic layer cover the protruding portion and are split apart below the protruding portion facing a wall surface of the eaves body.

Abstract: A semiconductor storage device includes a first stacked body, a second stacked body, a first division film, a second division film, and a plurality of discrete films. The a first stacked body includes first electrode layers stacked in a first direction. The second stacked body, above the first stacked body, includes second electrode layers stacked in the first direction. The second semiconductor layer is electrically connected to the first semiconductor layer. The first division film, extending in the first direction through the first stacked body, divides the first stacked body in a second direction crossing the first direction. The second division film, extending in the first direction through the second stacked body, divides the second stacked body in the second direction. The discrete films, extending in the first direction through the second stacked body, are disposed above the first division film.