Abstract: Provided are an MEMS device, a liquid ejecting head, a liquid ejecting apparatus, a manufacturing method of a MEMS device, a manufacturing method of a liquid ejecting head and a manufacturing method of a liquid ejecting apparatus. Provided is a MEMS device that includes a first substrate on which a flexibly deformable thin film member is laminated, a second substrate disposed at an interval with respect to the first substrate, and an adhesion layer that adheres the first substrate to the second substrate, in which an end of the thin film member extends to the outside of the end of the first substrate in an in-plane direction of the first substrate.

Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.

Abstract: A method for manufacturing semiconductor structure includes: providing a substrate having a first surface; forming a trench on the first surface, wherein a bottom surface and side walls of the substrate are configured along an outer periphery of the trench; annealing the substrate with high-purity argon or high-purity hydrogen to flatten the bottom surface and the side walls; conformally disposing a composite-material layer to cover the first surface, the bottom surface and the side walls; disposing a polysilicon material layer in the trench; removing the composite-material layer on the first surface; forming a multi-layer metal interconnection structure on the first surface and the polysilicon material layer, the multi-layer metal interconnection structure including a MEMS frame structure and through holes; removing the polysilicon material layer and the composite-material layer; using plasma treatment to the trench to flatten the bottom surface and the side walls. The plasma contains inert gas and hydrogen.

Abstract: A method of manufacturing a low temperature polysilicon thin film, including the steps of: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; roughening a surface of the silicon layer to form an uneven surface as a recrystallization growth space; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.

Abstract: A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide-containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.

Abstract: An electrostatic zipping actuator includes a primary electrode, a secondary electrode overlying the primary electrode, a dielectric layer located between and abutting at least a portion of the primary electrode and the secondary electrode, and a dielectric fluid disposed at least at a junction between the dielectric layer and one of the electrodes, where an average total thickness of the dielectric layer is less than approximately 10 micrometers.

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer having a first-type region and a second-type region that are stacked and interface with each other to form a p-n junction, the first-type region defining a first side of the semiconductor layer and the second-type region defining a second side of the semiconductor layer. The method further includes providing an insulating layer on the second side of the semiconductor layer and etching the semiconductor layer from the first side of the semiconductor layer toward the second side of the semiconductor layer to form a trench. The first-type region corresponds to one of a n-type region and a p-type region, and the second-type region corresponds to the other of the n-type region and the p-type region.

Abstract: A molecular machine comprising a movement part (2) including a first molecular element (4), a second molecular element (5), and a linking element (6) for constraining a relative movement of the first molecular element (4) and the second molecular element (5), and a control part configured to generate an electrical field around the movement part (2), wherein the first molecular element (4) is fixed relative to the control part, wherein the second molecular element (5) is movable relative to the first molecular element (4) in at least one degree of freedom, and wherein the second molecular element (5) is electrically charged such that the second molecular element (5) aligns to said electrical field.

Abstract: A method of manufacturing a low temperature polysilicon thin film, including: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; providing a mask; patterning the silicon layer through the mask, wherein the patterned silicon layer includes a plurality of recrystallization growth spaces; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.

Abstract: A sensor element including a diamond in which nitrogen-vacancy centers in a diamond crystal structure stabilize in a negative charge state. By ensuring that the diamond of the sensor element is n-type phosphorus-doped and contains nitrogen-vacancy centers in the crystal structure, the probability that nitrogen-vacancy centers in the diamond lattice are in a neutral state decreases, and the nitrogen-vacancy centers stabilize in a negative charge state.

Abstract: Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.

Abstract: Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.

Abstract: Provided are a method for preparing a silicon wafer with a rough surface and a silicon wafer, which solves the problem in the prior art that viscous force is likely to be generated. The method includes: depositing a first film layer having a large surface roughness on a surface of a silicon wafer that has been subjected to planar planarization, and then blanket etching the first film layer to remove the first film layer. Then, the surface of the first silicon layer facing away from the substrate is further etched to form grooves and protrusions, which provide roughness, thereby forming a silicon wafer with a rough surface. When the silicon wafer approaches to another film layer, the viscous force generated therebetween is reduced, and thus the sensitivity of the MEMS device is improved and the probability of out-of-work MEMS device is reduced.

Abstract: A method comprising: adhering a first surface of a mask to a carrier substrate via a first adhesive layer; forming a second adhesive layer on at least one of a second surface of the mask or a third surface of a wafer having a second alignment mark; bringing the carrier substrate and the wafer towards each other along a vertical axis such that the second surface of the mask and the third surface of the wafer is separated by an alignment gap based on a thickness of the second adhesive layer; performing an alignment operation based on imaging the first alignment mark and the second alignment mark; configuring the second surface of the mask to adhere to the third surface of the wafer via the second adhesive; and disconnecting the carrier substrate from the mask.

Abstract: A semiconductor device includes plural semiconductor fins and a gate structure over at least one of the semiconductor fins. The semiconductor fins have parallelogram top surfaces, and the parallelogram top surface has two acute interior angles and two obtuse interior angles. Two of the semiconductor fins are arranged along <110> crystallographic direction, and two of the semiconductor fins are arranged along <100> crystallographic direction.

Abstract: A load control system may include control devices for controlling power provided to an electrical load. The control devices may include a control-source device and a control-target device. The control-target device may control the power provided to the electrical load based on digital messages received from the control-source device. The control devices may include a load control discovery device capable of sending discovery messages configured to discover control devices within a location. The discovered control devices may be organized by signal strength and may be provided to a network device to enable association of the discovered control devices within a location. The discovery messages may be transmitted within an established discovery range. The discovery range may be adjusted to discover different control devices. Different control devices may be identified as the load control discovery device for discovering different control devices.

Abstract: A method and apparatus for achieving selective polarization states of emitted visible or other light in a stacked multicolor emissive display device by utilizing nonpolar, semipolar or strained c-plane crystallographic planes of semiconductor materials for light emitting structures within an electronic emissive display device.

Abstract: A micro-electro mechanical system (MEMS) device includes a MEMS substrate, at least one movable element laterally confined within a matrix layer that overlies the MEMS substrate, and a cap substrate bonded to the matrix layer through bonding material portions. A first movable element selected from the at least one movable element is located inside a first chamber that is laterally bounded by the matrix layer and vertically bounded by a first capping surface that overlies the first movable element. The first capping surface includes an array of downward-protruding bumps including respective portions of a dielectric material layer. Each of the downward-protruding bumps has a vertical cross-sectional profile of an inverted hillock. The MEMS device can include, for example, an accelerometer.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.