Abstract: A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters may detect a global maintenance command and send the global maintenance command to the command queue controller. The command queue controller may broadcast the global maintenance command to the clusters including the originating core's cluster. Each of the cores of the clusters may execute the global maintenance command. Each cluster may send an acknowledgement to the command queue controller upon completed execution of the global maintenance command by each core of the cluster. The command queue controller may also send, upon receiving an acknowledgement from each cluster, a final acknowledgement to the originating core's cluster.

Abstract: A method for data storage includes receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units. Respective estimates of a performance characteristic are obtained for the multiple memory units. A mapping, which maps the logical addresses to respective physical storage locations in the multiple memory units, is adapted based on the estimates so as to balance the performance characteristic across the memory units. The data items are stored in the physical storage locations in accordance with the adapted mapping.

Abstract: A mechanism is provided in a storage system for efficient inline data de-duplication. The mechanism receives a write command and a hash key for a portion of data to be written from an application host to a write address. The write command indicates whether the application host is tolerant or intolerant to data loss. Responsive to the write command indicating the application host is tolerant to data loss, the mechanism performs a hash key lookup in a hash index. The mechanism determines whether the portion of data has previously been written to the storage system. Responsive to determining the portion of data has previously been written to the storage system, the mechanism stores a pointer to the previously written data at the write address.

Abstract: Methods and systems for collecting and managing anesthesia perioperative data of a patient are provided. More particularly, a method of the present disclosure can include presenting a dashboard view of a user interface on a display of a computing device. The dashboard view can display a plurality of modules corresponding to the various perioperative periods of a procedure. In response to a user input, the method can access a module in the plurality of modules if it is determined that the user has access to the module, and can present a corresponding module interface.

Abstract: A system and method for efficient buffer management for banked shared memory designs are provided. In one embodiment, a controller within the switch is configured to manage the buffering of the shared memory banks by allocating full address sets to write sources. Each full address set that is allocated to a write source includes a number of memory addresses, wherein each memory address is associated with a different shared memory bank. A size of the full address set can be based on a determined number of buffer access contenders.

Abstract: Placement of object replicas in a distributed storage system includes, at a first instance, opening a journal for storage of object chunks. An object is received, which comprises one or more chunks. Each chunk comprises one or more storage blocks. The blocks for a single chunk are stored in a single journal. Global metadata for the object is stored, which includes a list of chunks for the object. Local metadata for the chunk is stored, which includes a block list identifying each block of the plurality of blocks. The local metadata is associated with the journal. The journal is later closed. The journal is subsequently replicated to a second instance. The global metadata is updated to reflect the replication, whereas the local metadata is unchanged by the replication.

Abstract: A method is used in managing storage space in storage systems. Metadata of a slice of a storage pool in a data storage system is evaluated for returning the slice as free storage to the storage pool. Based on the evaluation, returning of the slice to the storage pool is affected. The metadata of the slice indicates whether the slice includes user data.

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract: A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.

Abstract: Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.

Abstract: Processing I/O operations is described. A write operation writes first data to a first location on a logical device having a logical address space partitioned into extents. The first location is included in a first subrange of the logical address space. Each extent includes logical address subranges of the logical address space. The first subrange is one of the logical address subranges of a first extent of the logical device. Physical storage is allocated from a first physical device of a first write endurance classification of flash memory-based storage devices. The first write endurance classification is selected in accordance with a ranking of multiple write endurance classifications. The physical storage is mapped to the first subrange. The first data is stored on the allocated physical storage. First workload information for the first write endurance classification for the first extent is updated to reflect the first write operation.

Abstract: A data storage method, comprising, receiving host data to be written to a plurality of flash storage devices, allocating the host data to one or more data units of a plurality of data units, allocating pad data to one or more data units of the plurality of data units that have not been filled with host data and generating redundant data in a redundant data unit based on the plurality of data units. The method further comprises steps for writing the plurality of data units and the redundant data unit to a stripe across the plurality of flash storage devices, wherein each of the plurality of data units and the redundant data unit is written in the respective flash storage devices at a common physical address.

Abstract: Techniques for improving snapshot performance are disclosed. In one embodiment, the techniques may be realized as a method for improving snapshot performance comprising initiating change block tracking for each unit of storage associated with each of a plurality of virtual machines, creating backup images of each unit of storage associated with each of the plurality of virtual machines, quiescing each of the plurality of virtual machines, and creating snapshots of each unit of storage associated with each of the plurality of virtual machines. The techniques may include identifying one or more changed blocks in at least one of the backup images using the change block tracking, editing the at least one of the backup images by replacing the identified one or more changed blocks using corresponding blocks from at least one snapshot of the snapshots, and releasing the at least one snapshot based upon a determination that editing has completed.

Abstract: Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.

Abstract: Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

Abstract: A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.