Patents Examined by Yong Choe
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Patent number: 9348643Abstract: Transactional execution of a transaction beginning instruction initiates prefetching, by a CPU, of discontiguous storage locations specified by a list. The list includes entries specifying addresses and may also include corresponding metadata. The list may be specified by levels of indirection. Fetching of corresponding discontiguous cache lines is initiated while in TX mode. Additional instructions in the transaction may be executed and use the prefetched cache lines.Type: GrantFiled: June 30, 2014Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
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Patent number: 9348515Abstract: A storage apparatus comprises a storage device storing data which is read/written by a host computer and a control device for controlling data writing to the storage device. The control device provides a predetermined storage area of the storage device to the host computer as one or more volumes and, in response to the request from the management computer, provides statistical information relating to the storage areas to the management computer. the management computer comprises a storage device storing a storage area management table for managing the storage area of a plurality of storage apparatuses and a control device for managing the configuration of the storage areas of the storage apparatuses. The control device manages the data configuration of the plurality of storage apparatuses on the basis of the statistical information relating to the storage areas of the storage apparatuses which is provided by the plurality of storage apparatuses.Type: GrantFiled: March 22, 2011Date of Patent: May 24, 2016Assignee: Hitachi, Ltd.Inventors: Satoshi Kaneko, Akira Yamamoto, Tsukasa Shibayama
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Patent number: 9348756Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.Type: GrantFiled: October 24, 2014Date of Patent: May 24, 2016Assignee: IP Cube Partners (ICP) Co., Ltd.Inventor: Moon J. Kim
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Patent number: 9348761Abstract: Described are techniques that select a physical storage device for storing data. Device weights for physical storage devices are determined in accordance with factor(s) including a storage capacity each physical storage device and an amount of remaining write capacity of each physical storage device representing an amount of remaining writes for an expected lifetime of each physical storage device. A replica set is determined for each physical storage device in accordance with a device weight. Hash value sets are determined for the physical storage devices using a hash function. A first hash value for a first data item is determined using the hash function. The first hash value is mapped to a second hash value included in one of hash value sets associated with a corresponding one of the physical storage devices. The corresponding one of the physical storage devices is selected to store the first data item.Type: GrantFiled: June 30, 2014Date of Patent: May 24, 2016Assignee: EMC CorporationInventors: Daniel E. Cummins, Thomas E. Linnell
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Patent number: 9348785Abstract: Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a source configured to communicate signals to a memory device. At least one memory cube may coupled to the source by a communications link having more than one communications path. The memory cube may include a memory device operably coupled to a routing switch that selectively communicates the signals between the source and the memory device.Type: GrantFiled: February 17, 2014Date of Patent: May 24, 2016Assignee: Micron Technology, Inc.Inventor: David R. Resnick
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Patent number: 9342474Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.Type: GrantFiled: July 13, 2015Date of Patent: May 17, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Joseph D. Macri, Daniel L. Bouvier
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Patent number: 9336047Abstract: Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.Type: GrantFiled: June 30, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel
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Patent number: 9336152Abstract: Described herein are methods, systems and machine-readable media for simulating a FIFO cache using a Bloom filter ring, which includes a plurality of Bloom filters arranged in a circular log. New elements are registered in the Bloom filter at the head of the circular log. When the Bloom filter at the head of the circular log is filled to its capacity, membership information associated with old elements in the Bloom filter at the tail of the circular log is evicted (simulating FIFO cache behavior), and the head and tail of the log are advanced. The Bloom filter ring is used to determine cache statistics (e.g., cache hit, cache miss) of a FIFO cache of various sizes. In response to simulation output specifying cache statistics for FIFO cache of various sizes, a FIFO cache is optimally sized.Type: GrantFiled: January 20, 2016Date of Patent: May 10, 2016Assignee: Nimble Storage, Inc.Inventors: Senthil Kumar Ramamoorthy, Umesh Maheshwari
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Patent number: 9335947Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.Type: GrantFiled: June 30, 2014Date of Patent: May 10, 2016Assignee: RAYTHEON COMPANYInventors: Pen C. Chien, Frank N. Cheung, Kuan Y. Huang
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Patent number: 9330013Abstract: A method of cloning data in a memory for a source virtual machine (VM) and at least one cloned virtual machine is proposed. A mapping relationship between a guest physical address from the source VM or the cloned VM and a host physical address of the memory is defined by a plurality of page tables configured in a plurality of hierarchical levels. In the method, metadata of the page tables in the highest level or the higher levels of the plurality of hierarchical levels is copied to the virtual machine. Remaining metadata of the page tables in the levels other than the highest level or the higher levels of the plurality of hierarchical levels is replicated to the virtual machine in response to the access operation. Data stored in the corresponding address of the memory is accessed according to the metadata and the replicated metadata.Type: GrantFiled: June 28, 2012Date of Patent: May 3, 2016Assignee: Industrial Technology Research InstituteInventors: Han-Lin Li, Jui-Hao Chiang, Tzi-Cker Chiueh
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Patent number: 9330727Abstract: A method of determining whether a data object is stored on a storage device such as a disk includes a write operation that partitions the data object into sub-objects according to a random sequence of control bits, by (a) assigning a first block of the data object to an initially selected sub-object, and (b) assigning successive blocks to a currently selected sub-object or to a next selected sub-object based on the value of the corresponding control bit. The sub-objects are written to distinct physical regions of the storage device so that differential read latencies are experienced depending on the pattern of block access. An object read/verify operation includes reading the blocks of the data object sequentially, recording respective latencies, constructing a result word to record latency values, and calculating a difference between the control word and the result word.Type: GrantFiled: December 30, 2013Date of Patent: May 3, 2016Assignee: EMC CorporationInventor: Ari Juels
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Patent number: 9330020Abstract: Detailed herein are systems, apparatuses, and methods for transparent page level instruction translation. Exemplary embodiments include an instruction translation lookaside buffer (iTLB), wherein each iTLB entry includes a linear address of a page in memory, a physical address of the page in memory, and a remapping indicator.Type: GrantFiled: December 27, 2013Date of Patent: May 3, 2016Assignee: Intel CorporationInventors: Paul Caprioli, Vedvyas Shanbhogue, Koichi Yamada
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Patent number: 9323615Abstract: A method of distributing data in a distributed storage system includes receiving a file into non-transitory memory and dividing the received file into chunks. The chunks are data-chunks and non-data chunks. The method also includes grouping one or more of the data chunks and one or more of the non-data chunks in a group. One or more chunks of the group is capable of being reconstructed from other chunks of the group. The method also includes distributing the chunks of the group to storage devices of the distributed storage system based on a hierarchy of the distributed storage system. The hierarchy includes maintenance domains having active and inactive states, each storage device associated with a maintenance domain, the chunks of a group are distributed across multiple maintenance domains to maintain the ability to reconstruct chunks of the group when a maintenance domain is in an inactive state.Type: GrantFiled: January 31, 2014Date of Patent: April 26, 2016Assignee: Google Inc.Inventors: Robert Cypher, Sean Quinlan, Steven Robert Schirripa, Lidor Carmi, Christian Eric Schrock
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Patent number: 9323463Abstract: A first storage apparatus, on the basis of management information representing data existing in a virtual cache area, when a first data conforming to a read request exists in the virtual cache area, determines whether the first data is stored in a first cache area of the first storage apparatus. The first storage apparatus, when the first data is not stored in the first cache area, acquires the first data from a second cache area of a second storage apparatus, and transmits the first data to a host computer. The first storage apparatus, when the first data is associated with the first cache area on the basis of a degree of importance, notifies the second storage apparatus to that effect, and change an apparatus in charge of a cache of the first data of the management information from the second storage apparatus to the first storage apparatus.Type: GrantFiled: August 5, 2014Date of Patent: April 26, 2016Assignee: HITACHI, LTD.Inventor: Tsuyoshi Inoue
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Patent number: 9317431Abstract: An address generator includes a storage device in which one or more second-protocol-family address prefixes are stored, the one or more second-protocol-family address prefixes each corresponding to a corresponding combination of at least a multiplexing identifier and a first-protocol-family address, and a controller configured to read, from the storage device, the second-protocol-family address prefix corresponding to a combination of at least the multiplexing identifier and the first-protocol-family address that is contained in a data block to be transferred via a backbone network to a destination network which uses the first protocol family, the read second-protocol-family address prefix serving as an address prefix for a network that is overlaid with the destination network, and configured to generate a second-protocol-family address containing the first-protocol-family address, the multiplexing identifier, and the read second-protocol-family address prefix, the generated second-protocol-family address serType: GrantFiled: December 6, 2013Date of Patent: April 19, 2016Assignee: FUJITSU LIMITEDInventor: Naoki Matsuhira
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Patent number: 9317437Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.Type: GrantFiled: June 1, 2015Date of Patent: April 19, 2016Assignee: IP CUBE PARTNERS (ICP) CO., LTD.Inventor: Moon J. Kim
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Patent number: 9304693Abstract: Systems and methods for writing data to a data storage structure are provided. A data storage structure includes an array of storage locations. A plurality of write ports are configured to write a number of elements to the array simultaneously. The array of storage locations is arranged logically into N groups. Each group of the N groups is associated with a single multiplexer of a plurality of multiplexers. The single multiplexer is configured to receive inputs from the plurality of write ports and to select a single input to be written to a storage location of the associated group.Type: GrantFiled: December 5, 2013Date of Patent: April 5, 2016Assignee: Marvell International Ltd.Inventor: Kim Schuttenberg
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Patent number: 9304915Abstract: One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table.Type: GrantFiled: September 16, 2014Date of Patent: April 5, 2016Assignee: VMware, Inc.Inventors: Keith Adams, Sahil Rihan
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Patent number: 9298605Abstract: The subject technology discloses configurations for selecting a set of objects stored in volatile memory that have not been recently used by the application in which each object from among the set of object resides at a respective range of memory addresses in the volatile memory and each object was created by the application. Memory protection is set on the respective range of addresses in the volatile memory for each object from among the set of objects in which the memory protection flags the respective range of addresses for handling when the application subsequently performs a read or write operation to the respective range of addresses. The subject technology copies the set of objects from the volatile memory to a non-volatile memory. The respective range of memory addresses in the volatile memory are freed for each object from among the set of objects.Type: GrantFiled: July 31, 2013Date of Patent: March 29, 2016Assignee: Google Inc.Inventor: Kentaro Hara
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Patent number: 9298879Abstract: Methods and systems for collecting and managing anesthesia perioperative data of a patient are provided. More particularly, a method of the present disclosure can include presenting a dashboard view of a user interface on a display of a computing device. The dashboard view can display a plurality of modules corresponding to the various perioperative periods of a procedure. In response to a user input, the method can access a module in the plurality of modules if it is determined that the user has access to the module, and can present a corresponding module interface.Type: GrantFiled: August 1, 2013Date of Patent: March 29, 2016Inventors: Kenneth Ellington, Robert O'Brien, James Hurst