Patents Examined by Yong Choe
  • Patent number: 9620213
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: April 11, 2017
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9619149
    Abstract: Described are techniques that select a physical storage device for storing data. Device weights for physical storage devices are determined in accordance with factor(s) including a storage capacity each physical storage device and an amount of remaining write capacity of each physical storage device representing an amount of remaining writes for an expected lifetime of each physical storage device. A replica set is determined for each physical storage device in accordance with a device weight. Hash value sets are determined for the physical storage devices using a hash function. A first hash value for a first data item is determined using the hash function. The first hash value is mapped to a second hash value included in one of hash value sets associated with a corresponding one of the physical storage devices. The corresponding one of the physical storage devices is selected to store the first data item.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 11, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Daniel E. Cummins, Thomas E. Linnell
  • Patent number: 9612975
    Abstract: Embodiments of the inventive concept can include a multi-stage mapping technique for a page cache controller. For example, a gigantic virtual page address space can be mapped to a physical page address efficiently, both in terms of time and space. An internal mapping module can implement a mapping technique for kernel virtual page address caching. In some embodiments, the mapping module can include integrated balanced skip lists and page tables for mapping sparsely populated kernel virtual page address space or spaces to physical block (i.e., page) address space or spaces. The mapping module can automatically and dynamically convert one or more sections from a skip list to a page table, or from a page table to a skip list. Thus, the kernel page cache can be extended to have larger secondary memory using volatile or non-volatile page cache storage media.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: ZiHui (Jason) Li
  • Patent number: 9612957
    Abstract: Systems, methods, and apparatus are herein disclosed for reducing read disturb and data retention errors in FLASH memory devices designed for long lifespans, such as greater than 10 or 15 years. Read disturb errors can be reduced by maintaining a read counter stored in a volatile memory and a FASTMAP memory block of the FLASH memory. When the read counter meets a threshold, then the associated memory block can be scheduled for scrubbing. Data retentions errors can be reduced by maintaining a last-erase timestamp in metadata of each memory block of a FLASH memory. When the last-erase timestamp associated with a given memory block meets a threshold, then the memory block can be scheduled for scrubbing.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 4, 2017
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Tatyana Brokhman, Konstantin Dorfman
  • Patent number: 9613036
    Abstract: A first system adaptation unit of magnetic tape drive apparatus communicates with a read/write request source based on a method adapted to a file system. A second system adaptation unit communicates data with the read/write request source based on a method adapted to a designated system other than the file system. A control unit allows the first system adaptation unit to be in a ready state when a format of a magnetic tape to be read and written is adapted to the file system and allows otherwise the first system adaptation unit to be in a not-ready state. The control unit deceives the read/write request source as if the first system adaptation unit is in the ready state even when the first system adaptation unit is in the not-ready state as well as the ready state.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: April 4, 2017
    Assignee: NEC CORPORATION
    Inventors: Makoto Nakajima, Hajime Nonaka, Muneyuki Yoshikawa, Yuuki Hayakawa
  • Patent number: 9606740
    Abstract: A system, method and computer program product for synchronizing data written to tape with improved data recovery. When writing data to tape, an index is kept in memory and updated to reflect change(s) to a file system mounted on tape. After a predetermined amount of data is written to a tape, a device may perform a sync operation, causing the index to be written into a data partition of the tape. If the sync operation is successful, the index in the index partition of the tape can be updated using a copy of the index in the data partition of the tape next time the tape is mounted. If the sync operation is not successful, the device may write the data to a different location on the same or another tape, update the index, and force another sync operation. This process can be repeated.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 28, 2017
    Assignee: KIP CR P1 LP
    Inventors: Andrew Glen Klein, Robert C. Sims, William H. Moody, II
  • Patent number: 9606745
    Abstract: In conventional unified storage systems, an I/O for block storage and an I/O for file storage are processed in a single OS without being distinguished, so that it was not possible to perform processes for speedy failure detection or for enhancing performances such as tuning of performance by directly monitoring hardware. The present invention solves the problem by having a block storage-side OS and an OS group managing multiple systems including a file system other than the block storage-side OS coexist within a storage system, wherein the OS group managing multiple systems including a file system other than the block storage-side OS is virtualized by a hypervisor, wherein a block storage micro-controller and the hypervisor can cooperate in performing processes.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: March 28, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Ai Satoyama, Yoshiaki Eguchi
  • Patent number: 9575668
    Abstract: Processing I/O operations is described. A write operation writes first data to a first location on a logical device having a logical address space partitioned into extents. The first location is included in a first subrange of the logical address space. Each extent includes logical address subranges of the logical address space. The first subrange is one of the logical address subranges of a first extent of the logical device. Physical storage is allocated from a first physical device of a first write endurance classification of flash memory-based storage devices. The first write endurance classification is selected in accordance with a ranking of multiple write endurance classifications. The physical storage is mapped to the first subrange. The first data is stored on the allocated physical storage. First workload information for the first write endurance classification for the first extent is updated to reflect the first write operation.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 21, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: Owen Martin
  • Patent number: 9575672
    Abstract: A storage system has a plurality of flash packages, and a storage controller for receiving a write request from a host and sending a write-data write request based on data conforming to this write request to a write-destination flash package. A virtual capacity, which is larger than the physical capacity of the flash package, is defined in the storage controller. The storage system compresses the write data, and writes the compressed write data to the write-destination flash chip.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 21, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Masayuki Yamamoto
  • Patent number: 9575663
    Abstract: A solid state drive in accordance with embodiments of the present inventive concepts may include a nonvolatile memory, a volatile memory, a memory controller controlling the nonvolatile memory and the volatile memory, and a power generator providing power to the nonvolatile memory, the volatile memory, and the memory controller. A method of operating the solid state drive may include designating a bank that will perform a self refresh among a plurality of banks included in the volatile memory in response to a power saving mode signal. Information of the designated bank may be stored in a register in response to a command and an address signal; and a self refresh of the designated bank may be performed on the basis of the information stored in the register.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In Bo Shim
  • Patent number: 9575661
    Abstract: Systems and methods of determining a similarity between data units in a nonvolatile memory are disclosed. One method includes obtaining first and second data units and dividing the first and second data units into a first plurality of non-overlapping chunks of data and a second plurality of non-overlapping chunks of data. The method further includes determining a first plurality of values and a second plurality of values associated with the chunks, and determining a similarity between the first second data units based on the first plurality values and of the second plurality of values. In one example embodiment, a similarity between an incoming data unit and another data unit is determined based on the number of buckets storing an incoming index value and another index value associated with the another data unit. A plurality of buckets in a table is determined based on a selected plurality of hash values.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Avner Dor, Elona Erez, Jun Jin Kong
  • Patent number: 9575675
    Abstract: Methods, apparatus and computer program products for a distributed system include dividing logical volume data into data subsets, and defining at least one distributedly storage configuration for the logical volume. Metadata for the logical volume is written to a first set of first metadata tables, and the first set of first metadata tables is divided into metadata subsets having a one-to-one correspondence with the data subsets. The metadata subsets are distributed among the multiple digital information devices, and the metadata is copied from the first set of first metadata tables to a second set of corresponding second metadata tables in a one-to-one correspondence with the first metadata tables.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Chambliss, Ehood Garmiza, Leah Shalev, Eliyahu Weissbrem
  • Patent number: 9576624
    Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: February 21, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nicholas Odin Lien, Ara Patapoutian, Jeffrey J. Pream, Young Pil Kim, David Orrin Sluiter
  • Patent number: 9575669
    Abstract: A memory controller and method for scheduling commands in a memory controller are disclosed. A programmable solid state drive (SSD) controller and a non-volatile memory apparatus are provided. Data structures, termed “Superbufs” are utilized for organizing internal activities in the SSD controller. Each data structure can comprise a host command area, a command area, and a notes or scratch pad area. A memory controller can be configured to, upon receiving a host command, copy the original received host command into the host command area of a first data structure, generate a first command group, copy the first command group into the command area, and execute commands of the first command group. A data structure can be initialized to an idle state, and can transition to other states such as a new command received state, a read for execution state, a command group complete state and an error state.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 21, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ashish Singhai, Kenneth Alan Okin
  • Patent number: 9564960
    Abstract: In a satellite communication system comprising at least a hub and a plurality of terminals, at least one terminal may include a cache for storing data objects. The cache may be based on a detachable memory device that may be inserted to or removed from the terminal at any given time, including after the terminal is deployed. Aspects are directed to preventing a prefetching of objects already stored in a cache of a remote terminal. In some embodiments, an efficient multicasting of content to terminals over an adaptive link may occur in a manner which may benefit terminals comprising a cache while not affecting or minimally affecting the performance of terminals that may not include a cache.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: February 7, 2017
    Assignee: Gilat Satellite Networks Ltd.
    Inventors: Oren Markovitz, Yoseph Hecht, Nitay Argov, Zohar Kanfi
  • Patent number: 9563361
    Abstract: A processor-implemented method for copying a source file to a destination file using a virtual memory manager (VMM) of a computer operating system is provided. The method includes receiving, by the VMM, a request to copy the source file to a destination file. The method further provides that based on the status of the virtual page, performing at least one of moving the virtual page to the destination file, copying the virtual page to the destination file, reading the virtual page into memory, and ignoring the virtual page.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Ninad S. Palsule
  • Patent number: 9563481
    Abstract: A method, apparatus, and computer program product are provided in a data processing system for performing a logical partition migration utilizing multiple mover service partition pairs. Responsive to a virtual machine monitor initiating a logical partition migration operation to move a logical partition from a source system to a destination system, a plurality of input/output paths are established between a plurality of mover service partition pairs. The virtual machine monitor performs the logical partition migration operation using the plurality of mover service partition pairs to transfer a memory image of the logical partition from the source system to the destination system to effect the logical partition migration operation. Responsive to failure of one of the plurality of input/output paths, the virtual machine monitor may complete the logical partition migration operation using at least one remaining mover service partition pair.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Maria D. Garza, Neal R. Marion, Nathaniel S. Tomsic, Vasu Vallabhaneni
  • Patent number: 9558121
    Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 31, 2017
    Assignee: INTEL CORPORATION
    Inventors: Li-Gao Zei, Fernando Latorre, Steffen Kosinski, Jaroslaw Topp, Varun Mohandru, Lutz Naethke
  • Patent number: 9552327
    Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 24, 2017
    Assignee: KnuEdge Incorporated
    Inventors: Douglas A. Palmer, Ramon Zuniga
  • Patent number: 9552298
    Abstract: Methods and systems configured to facilitate smart pre-fetching for sequentially accessing tree structures such as balanced trees (b-trees) are described herein. According to various described embodiments, a pre-fetch condition can be determined to have been met for a first cache associated with a first level of a tree such as a b-tree. A link to a bock of data to be read into the cache can be read into the cache by accessing a second level of the tree. The data elements associated with the retrieved link can subsequently read into the cache.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 24, 2017
    Assignee: Sybase, Inc.
    Inventors: Shailesh Mungikar, Blaine French