Patents Examined by Yong J. Choe
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Patent number: 11907534Abstract: A storage device projected temperature environment configuration system includes storage devices with the same physical hardware configuration, and a computing device manufacturing system that manufactures computing devices.Type: GrantFiled: August 31, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventors: Anthony Gerard Ginty, Gregory Martin Allen
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Patent number: 11899975Abstract: A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.Type: GrantFiled: January 28, 2022Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventor: Chinnakrishnan Ballapuram
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Patent number: 11893237Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: February 3, 2022Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 11893257Abstract: A system may include a memory and a processor in communication with the memory configured to perform operations. The may operations include obtaining transaction logs in blocks from nodes of a data storage system. The operations may include, for each transaction log, splitting the transaction log into log entries, grouping log entries into groups associated with a same data source, and writing the log entries of the groups to empty blocks such that log entries from different groups do not share a same block. The operations may include identifying a same sequence of log entries from the written transaction logs and uploading first blocks of a first transaction log, including the same sequence of log entries, to an object-based storage without uploading second blocks of a second transaction log including the same sequence of log entries to the object-based storage.Type: GrantFiled: June 15, 2022Date of Patent: February 6, 2024Assignee: International Business Machines CorporationInventors: Peng Hui Jiang, FengLi Wang, Qi Feng Huo, Jun Su, Hong Qing Zhou, Yan Lin Ren, Li Zhang, Ling Ling Sh Hu
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Patent number: 11886348Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.Type: GrantFiled: March 6, 2023Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Laurent Isenegger, Robert M. Walker, Cagdas Dirik
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Patent number: 11886702Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.Type: GrantFiled: January 26, 2022Date of Patent: January 30, 2024Assignee: Micron Technology, Inc.Inventors: Eric V. Pohlmann, Neal J. Koyle
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Patent number: 11880568Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.Type: GrantFiled: December 28, 2021Date of Patent: January 23, 2024Assignee: SEAGATE TECHNOLOGY LLCInventors: Rajesh Maruti Bhagwat, Nahoosh Hemchandra Mandlik, Niranjan Anant Pol, Hemantkumar Vitthalrao Mane
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Patent number: 11861221Abstract: Providing scalable and reliable container-based storage services, including: deploying a containerized storage controller on a first node among of plurality of nodes operable to support execution of the containerized storage controller; associating a dataset stored in backing storage accessible by the first node with one or more virtualized volumes presented by the containerized storage controller; and providing, by the containerized storage controller to one or more client hosts, a set of storage services for the one or more virtualized volumes.Type: GrantFiled: April 6, 2021Date of Patent: January 2, 2024Assignee: PURE STORAGE, INC.Inventors: Michael Richardson, Ronald Karr
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Patent number: 11853266Abstract: A system for cloud-based file services, comprising: a plurality of single-tenant file system nodes configured to provide file system access to an object store via a plurality of multitenant storage nodes; the plurality of multitenant storage nodes sharing access to the object store; and one or more management nodes configured to provision resources for the plurality of single-tenant file system nodes and the plurality of multitenant storage nodes, including modifying resources within the system.Type: GrantFiled: July 18, 2022Date of Patent: December 26, 2023Assignee: PURE STORAGE, INC.Inventors: Robert Lee, Igor Ostrovsky, Mark Emberson, Boris Feigin, Ronald Karr
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Patent number: 11853583Abstract: A method of managing data storage using a management device that includes determining respective status information for a plurality of storage devices, and calculating, based on the status information, a respective cost for each of the plurality of storage devices using a cost function that includes one or more parameters including at least one of: a program/erase (P/E) parameter, a block error state parameter, a block error level parameter, and a workload parameter. The method further includes selecting a destination storage device of the plurality of storage devices based on at least some of the calculated costs, and writing data to the destination storage device.Type: GrantFiled: November 8, 2021Date of Patent: December 26, 2023Assignee: KIOXIA CORPORATIONInventor: Yaron Klein
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Patent number: 11842068Abstract: Systems and methods are described for using a Deep Reinforcement Learning (DRL) agent to automatically tune Quality of Service (QoS) settings of a distributed storage system (DSS). According to one embodiment, a DRL agent is trained in a simulated environment to select QoS settings (e.g., a value of one or more of a minimum IOPS parameter, a maximum IOPS parameter, and a burst IOPS parameter). The training may involve placing the DRL agent into every feasible state representing combinations of QoS settings, workload conditions, and system metrics for a period of time for multiple iterations, and rewarding the DRL agent for selecting QoS settings that minimize an objective function based on a selected measure of system load. The trained DRL agent may then be deployed to one or more DSSs to constantly update QoS settings so as to minimize the selected measure of system load.Type: GrantFiled: June 16, 2022Date of Patent: December 12, 2023Assignee: NetApp, Inc.Inventor: Tyler W. Cady
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Patent number: 11842083Abstract: In a storage system architecture having two storage virtualization controllers (SVCs) that operate in an active-active mode, the corresponding relationships between storage addresses in the two buffers of the two SVCs are pre-determined. When a non-owner SVC that does not have an ownership over a logical disk (LD), receives an I/O request from a host, the non-owner SVC will inquire of the other SVC having the ownership, about associated address information, and then the non-owner SVC that does not have the ownership over the LD will perform, according to the associated address information, the I/O request from the host. Therefore, data synchronization operation for mutually backing up data between the two SVCs can be fast achieved. Also, it allows the host to issue a data access request to any one of the SVCs, thus improving performance of the storage system.Type: GrantFiled: January 25, 2022Date of Patent: December 12, 2023Assignee: Infortrend Technology, Inc.Inventor: Yun-Jian Lo
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Patent number: 11836357Abstract: Optimizing copy operations in a storage array, includes combining, in dependence upon a metadata optimization policy, a plurality of copy operations into a single copy operation and splitting the single copy operation into an optimized set of executable copy operations that copy data based on memory alignment.Type: GrantFiled: April 28, 2022Date of Patent: December 5, 2023Assignee: PURE STORAGE, INC.Inventors: Christopher Golden, Scott Smith, Luke Paulsen, David Grunwald, Jianting Cao
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Patent number: 11836613Abstract: Methods and systems for generating a program include parameterizing a high-order function to replace data with primitive functions. A neural programmer interpreter (NPI) model is trained for the high-order function. Respective neural network models are trained for each primitive function. The neural network models generate data for the NPI model when called.Type: GrantFiled: July 17, 2019Date of Patent: December 5, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Tung D. Le
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Patent number: 11829601Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.Type: GrantFiled: January 9, 2023Date of Patent: November 28, 2023Assignee: Memory Technologies LLCInventors: Jani Hyvonen, Kimmo J. Mylly, Jussi Hakkinen, Yevgen Gyl
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Patent number: 11822797Abstract: An object computational storage system, a data processing method, a client end and a storage medium are disclosed, belonging to the field of electrical digital data processing, including a storage control device and a storage chip or a storage disk connected thereto. The storage control device is a computational storage management system, and performs the following processing: receiving an external data processing request, parsing information of a specified storage object, information of a specified function, and information of input data carried by the data processing request; when it is determined that calling the specified function for the specified storage object is supported, calling the specified function to perform computation on data of the specified storage object according to the input data; and returning a computation result to a sender of the data processing request.Type: GrantFiled: April 20, 2023Date of Patent: November 21, 2023Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGYInventors: Jin Dai, Yunsen Zhang
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Patent number: 11816027Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a request for garbage collection, identify a range of physical blocks in a storage device, query a bitmap, the bitmap having a bit for each physical block in the range of physical blocks, determine a status associated with a first bit from the bitmap, in response to determining the status associated with the first bit is a first state, add a first physical block associated with the first bit to a list of physical blocks for relocation, and relocate the list of physical blocks.Type: GrantFiled: December 23, 2021Date of Patent: November 14, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ajith Kumar Battaje, Tanay Goel, Rajendra Prasad Mishra
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Patent number: 11816563Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.Type: GrantFiled: May 10, 2019Date of Patent: November 14, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Borna J. Obradovic, Engin Ipek
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Patent number: 11803321Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.Type: GrantFiled: September 12, 2022Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Horia C. Simionescu, Rohitkumar Makhija, Peng-Cheng Chen, Jung Sheng Hoei
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Patent number: 11789654Abstract: A data storage device and method for file-based interrupt coalescing are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to execute a plurality of read commands read from a submission queue in a host; write a plurality of completion messages to a completion queue in the host; and coalesce interrupts to inform the host that plurality of completion messages were written to the completion queue; wherein the submission queue and the completion queue are dedicated to read commands from a host application and are separate from a submission queue and a completion queue for read and write commands from an operating system of the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: September 29, 2021Date of Patent: October 17, 2023Assignee: Western Digital Technologies, Inc.Inventors: Judah Gamliel Hahn, Shay Benisty, Ariel Navon