Patents Examined by Young T. Tse
  • Patent number: 11831473
    Abstract: Reduced-complexity maximum likelihood sequence detectors (rMLSD) are disclosed for detecting multibit symbols such as those found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points. One illustrative digital communications receiver includes: an initial equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and a rMLSD that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: November 28, 2023
    Assignee: Credo Technology Group Limited
    Inventors: Yu Liao, Junqing (Phil) Sun
  • Patent number: 11817897
    Abstract: Embodiments provide a terminal point of a communication system, wherein a control signal is emitted in the communication system for coordinating the participants of the communication system, wherein the control signal is transferred distributed in correspondence with a frequency hop-based occupancy of resources of the frequency band, indicated by a control signal hopping pattern, wherein the terminal point has a receiver, wherein a receive bandwidth of the receiver is smaller at least by the factor 3 than a bandwidth of the frequency hop-based occupancy of resources of the frequency band, indicated by the control signal hopping pattern, wherein the terminal point is configured to receive a reference signal, the reference signal having information on the control signal, wherein the terminal point is configured to receive the control signal based on the information on the control signal.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 14, 2023
    Inventors: Gerd Kilian, Josef Bernhard, Frank Obernosterer, Raimund Meyer, Johannes Wechsler, Jakob Kneißl, Dominik Soller, Jörg Robert
  • Patent number: 11811438
    Abstract: Systems and methods for magnitude and phase trimming are provided. In one aspect, a radio frequency (RF) trimmer circuit includes an input terminal configured to receive an RF signal, an output terminal configured to output the RF signal, a control input configured to receive a control signal, at least one impedance element, and at least one transistor configured to selectively connect the impedance element onto a path between the input and output terminals. The selectively connecting the impedance element controls at least one of a magnitude trim and a phase trim of the RF signal.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 7, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: John Jackson Nisbet, Hassan Sarbishaei, Guillaume Alexandre Blin
  • Patent number: 11804991
    Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: October 31, 2023
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ting Liu, Che-Yu Chiang, Deng-Fu Weng
  • Patent number: 11802898
    Abstract: Embodiments provide a method, apparatus and device of reconstructing non-Kronecker structured channels, applicable to communications. A weight matrix is determined for emulating link characteristics of a reconstructed channel, and includes a weight corresponding to each ray mapped to a probe antenna. In each cluster, rays mapped to each probe antenna have different weights with each other. For each cluster, a time-varying fading channel impulse response of each ray of the cluster mapped to a probe antenna is calculated using the weight matrix. The time-varying fading channel impulse response includes a transition equation for each probe antenna describing mapping of rays of the cluster to the probe antenna. A transition matrix from each probe antenna to receiving antennas of a device under test is determined. A product of the time-varying fading channel impulse response of the cluster multiplied by the transition matrix serves as a channel impulse response of the cluster.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 31, 2023
    Assignee: Beijing University of Posts and Telecommunications
    Inventors: Yong Li, Wenbo Wang, Mugen Peng
  • Patent number: 11799696
    Abstract: A transceiver of the present inventive concept includes a transmitter and a receiver connected by a first line and a second line, and the transmitter includes a first encoder; a second encoder; and a transmission driver. The first encoder generates a first encoded data different from a first data during a first period and the second encoder generates a second encoded data equal to a second data during the first period, the second encoder generates the second encoded data different from the second data during a second period and the first encoder generates the first encoded data equal to the first data during the second period, and the first period and the second period are arranged to alternate with each other.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: October 24, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Suk Jung, Weon Jun Choe, Heen Dol Kim, Chae Hee Park, Ji Ye Lee
  • Patent number: 11792053
    Abstract: A method of realization of adaptive equalization and an adaptive equalizer. The adaptive equalizer comprises an equalizer unit, which is used for equaling an input signal according to a compensation coefficient to obtain an output signal; a sampling comparison unit, which is connected to an output of the equalizer and is used for sampling a comparison result of the output signal of the equalizer and a reference voltage corresponding to reference voltage step; a data processing unit, which is connected to the sampling comparison unit and the equalizer unit. It is used for scanning a reference voltage step to determine range of the reference voltage steps to which step the amplitude of the output signal is corresponding; and scanning a compensation coefficient step, and determining the compensation coefficient for equalization according to the range of reference voltage steps.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: October 17, 2023
    Assignee: EverPro Technologies Company Limited
    Inventors: Liang Xu, Yan Li, Jinfeng Tian, Yufeng Cheng, Yanan Chen
  • Patent number: 11784857
    Abstract: Various embodiments relate to an adaptive linear driver, including: a continuous time linear equalizer (CTLE); a programmable transmit driver coupled with an output of the CTLE, wherein the transmit driver includes a first control port configured to receive a first control signal configured to adjust the output level of the programmable transmit driver; an output comparator coupled to an output of the programmable transmit driver, wherein the output comparator is configured to compare the output of the programmable transmit driver with a reference signal and to produce a first comparison signal; and a controller coupled to the output comparator and the first control port, wherein the controller produces a first control signal based upon the first comparison signal.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: October 10, 2023
    Assignee: NXP USA, Inc.
    Inventors: Siamak Delshadpour, Peng Yan
  • Patent number: 11777406
    Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 3, 2023
    Inventors: Tawen Mei, Karen Huimun Chan
  • Patent number: 11770274
    Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: September 26, 2023
    Assignee: Apple Inc.
    Inventors: Wing Liu, Sanjeev K. Maheshwari
  • Patent number: 11770275
    Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: September 26, 2023
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
  • Patent number: 11765002
    Abstract: A method of equalizing a communication link includes setting a number of coefficients to a required number, determining a number of pulse responses for a waveform, setting all values in a set of values to zero, repeating, until all values have been assigned, determining a current lowest parameter, using a position of the current lowest parameter as an index, determining a minimum value between a first term multiplied by a main pulse response minus a summation of each parameter multiplied by each value, divided by the current lowest parameter, and a corresponding pulse response, and assigning the minimum value to the value having a position equal to the position of the current lowest parameter, and determining a value of each coefficient in a set of coefficients by multiplying each value with the sign of a corresponding pulse response; defining an equalizer having a number of taps having a value based on the corresponding coefficient; and applying the equalizer to a waveform.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: September 19, 2023
    Assignee: Tektronix, Inc.
    Inventor: Kan Tan
  • Patent number: 11764822
    Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 19, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Christopher Mayer, Manish J. Manglani
  • Patent number: 11757683
    Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: September 12, 2023
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Daeho Yun, Deog-Kyoon Jeong
  • Patent number: 11757681
    Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventors: Jose A. Tierno, Haiming Jin, Brian S. Leibowitz, Sanjeev K. Maheshwari, Chintan S. Thakkar
  • Patent number: 11750360
    Abstract: An apparatus includes a radio frequency (RF) receiver to receive packets. The RF receiver includes first and second synchronization field detectors (SFDs). The first and second SFDs detect synchronization headers generated using first and second physical layer (PHY) modes, respectively.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 5, 2023
    Assignee: Silicon Laboratories Inc.
    Inventors: Hendricus de Ruijter, Wentao Li, Lauri Mikael Hintsala
  • Patent number: 11742880
    Abstract: A radio frequency (RF) switch system, an RF switch protective circuit, and a protecting method thereof are provided. The RF switch system may include an RF switch and a protective circuit. The RF switch may be connected between a port that receives an RF signal and a ground. The protective circuit may detect a first voltage that is a voltage that is generated when the first RF switch is turned off, and may transmit an impedance value that is varied based on the first voltage to the port.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 29, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jongmo Lim, Wonsun Hwang, Byeonghak Jo, Yoosam Na, Youngsik Hur
  • Patent number: 11736266
    Abstract: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: August 22, 2023
    Assignee: Diodes Incorporated
    Inventors: Yu-Wei Lin, Yi Sheng Lin, Nanyuan Chen
  • Patent number: 11722170
    Abstract: Aspects presented herein may enable a UE to determine whether phase continuity is to be maintained for one or more uplink transmissions when the UE is configured with a frequency-hopping with zero frequency offset. In one aspect, a UE receives, from a network entity, an indication of frequency hopping with zero frequency offset. The UE determines whether phase continuity is to be applied to UL transmissions based on the indication of the frequency hopping with zero frequency offset. The UE transmits, to the network entity, at least one uplink channel with no phase continuity based on the determination to not apply phase continuity to the UL transmissions.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: August 8, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Mahmoud Taherzadeh Boroujeni, Peter Gaal, Hung Dinh Ly, Gokul Sridharan, Tao Luo
  • Patent number: 11711139
    Abstract: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: July 25, 2023
    Assignee: SEAKR Engineering, Inc.
    Inventors: Paul Rutt, Erik Buehler, Damon Van Buren