Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.

Abstract: There is provided a heat treatment apparatus, including: a processing container configured to perform a heat treatment on substrates accommodated in the processing container; a heating unit configured to cover an outer circumference of the processing container with a predetermined space defined the heating unit and the processing container; a discharge pipe installed outside of the processing container and within the predetermined space, and configured to communicate with an interior of the processing container to discharge an exhaust gas from the interior of the processing container; and a heat insulating member configured to cover a circumference of the discharge pipe.

Abstract: A method of forming a coating film over a substrate is provided. The method includes spinning the substrate. The method further includes providing a central coating liquid spray over a central portion of the substrate. The method also includes providing first coating liquid sprays over the substrate. The first coating liquid sprays surround the central coating liquid spray and are spaced apart from the central coating liquid spray by a same first distance.

Abstract: An organic light emitting diode (OLED) display including a display substrate; a sealing member facing the display substrate; a sealant between the display substrate and the sealing member, the sealant cohering the display substrate and the sealing member; a plurality of conductive wires on the display substrate and overlapping the sealant; and a heat blocking film between the conductive wire and the sealant, the heat blocking film including a plurality of sub-heat blocking films.

Abstract: A manufacturing method and a manufacturing equipment of a thin film transistor substrate are provided. In the manufacturing method, after forming a gate and a gate insulating layer of a thin film transistor, a semiconductor layer and a first protection layer are sequentially deposited. After patterning the first protection layer, the patterned first protection layer is used as a mask to pattern the semiconductor layer to form a semiconductor channel of the thin film transistor. By the above solution, the invention can reduce the number of mask and therefore is beneficial to reduce the cost.

Abstract: Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.

Abstract: The chip bonding apparatus used in a chip bonding method includes a heating unit for heating an anisotropic conductive film at a first temperature; an attachment unit for attaching an integrated circuit chip to the anisotropic conductive film; a stage on which a substrate is seated; a chip transport unit for moving and aligning the integrated circuit chip that is attached to the anisotropic conductive film on the substrate; and a bonding head arranged above the stage to bond the integrated circuit chip that is attached to the anisotropic conductive film onto the substrate through thermo-compression of the integrated circuit chip onto the substrate at a second temperature that is lower than the first temperature.

Abstract: The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.

Abstract: A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes an accommodation module configured to accommodate a substrate. The apparatus further includes a first flow channel including first openings configured to emit a first gas into the accommodation module. The apparatus further includes a second flow channel including second openings configured to emit the first gas into the accommodation module, a number or a size of the second openings being different from a number or a size of the first openings. The apparatus further includes a controller configured to control supplying of the first gas to the first and second flow channels such that the first gas is emitted from the first openings at a first flow velocity and the first gas is emitted from the second openings at a second flow velocity different from the first flow velocity.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: After embedding a silicon oxide film within a second trench that opens in a semiconductor substrate using a silicon nitride film as a hard mask, the silicon oxide film over the silicon nitride film is polished, and then, wet etching is performed before a step for removing the silicon nitride film, and thereby the upper surface of the silicon oxide film within a first trench opened in the silicon nitride film is retreated.

Abstract: The present invention provides an EEPROM core structure embedded into BCD process and forming method thereof. The EEPROM core structure embedded into BCD process comprises a selection transistor and a storage transistor connected in series, wherein the selection transistor is an LDNMOS transistor. The present invention may embed the procedure for forming the EEPROM core structure into the BCD process, which is favorable to reduce the complexity of the process.

Abstract: A method of manufacturing a nanostructure semiconductor light emitting device may includes preparing a mask layer by sequentially forming a first insulating layer and a second insulating layer on a base layer configured of a first conductivity-type semiconductor, forming a plurality of openings penetrating the mask layer, growing a plurality of nanorods in the plurality of openings, removing the second insulating layer, preparing a plurality of nanocores by re-growing the plurality of nanorods, and forming nanoscale light emitting structures by sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores. The plurality of openings may respectively include a mold region located in the second insulating layer, and the mold region includes at least one curved portion of which an inclination of a side surface varies according to proximity to the first insulating layer.

Abstract: An array substrate, a display device comprising the array substrate and a method of manufacturing the array substrate are provided.

Abstract: A method for manufacturing a semiconductor light emitting device may include steps of forming a mask layer and a mold layer having a plurality of openings exposing portions of a base layer, forming a plurality of first conductivity-type semiconductor cores each including a body portion extending through each of the openings from the base layer and a tip portion disposed on the body portion and having a conical shape, and forming an active layer and a second conductivity-type semiconductor layer on each of the plurality of first conductivity-type semiconductor cores. The step of forming the plurality of first conductivity-type semiconductor cores may include forming a first region such that a vertex of the tip portion is positioned on a central vertical axis of the body portion, removing the mold layer, and forming an additional growth region on the first region such that the body portion has a hexagonal prism shape.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP capacitor includes a first polysilicon layer, a metallic silicide layer, a protective layer, a dielectric layer, and a second polysilicon layer, which have a lower conductive plate pattern and are successively arranged. The method includes: providing a substrate; successively forming a first polysilicon layer, a metallic silicide, and a protective layer on the substrate; transferring a lower conductive plate pattern into the first polysilicon layer, the metallic silicide layer, and the protective layer, thus forming the first polysilicon layer, the metallic silicide layer, and the protective layer having the lower conductive plate pattern; successively forming a dielectric layer and a second polysilicon layer having a lower conductive plate pattern on the protective layer. The capacitance and reliability of the PIP capacitor are improved.

Abstract: A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead frame. A lead frame includes a plurality of connected units, each unit including a pair of lead portions arranged spaced apart and opposite from each other, for mounting a semiconductor element and electrically connecting to a pair of electrodes of the semiconductor element respectively. The lead portions respectively include an element mounting region arranged on a surface thereof to mount the semiconductor element, and a groove extending from opposing end surfaces of each of the pair of lead portions, in a direction away from the end surfaces and bending in a surrounding manner along outer periphery of the element mounting region.

Abstract: An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N? type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N? epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N? type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector.

Abstract: The present invention provides a quantum rod including a core including zinc compound; and a shell covering the core and including ZnS. The quantum rod emits the short wavelength light.