Abstract: The method includes disposing semiconductor chips on a package substrate having sawing lines, forming an encapsulant to cover the semiconductor chips on the package substrate, forming a package assembly by a first curing of the encapsulant, forming first grooves by cutting the encapsulant along the sawing lines, performing a second curing of the encapsulant, and dividing the package assembly into unit semiconductor packages by cutting the package substrate along the sawing lines and forming second grooves to overlap the first grooves.

Abstract: A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

Abstract: The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer.

Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: The present invention provides a method for manufacturing a solid electrolytic capacitor element, wherein a dielectric layer, a semiconductor layer, a carbon layer and a silver layer are sequentially formed on a tungsten base material. This method is characterized in that: the formation of the carbon layer is carried out by laminating a carbon paste on the semiconductor layer; the carbon paste is an aqueous resin solution containing carbon particles; and a repair formation treatment is carried out after the formation of the carbon layer but before the formation of the silver layer. The time duration of the repair formation treatment is 1-40 minutes; the current density is 0.05-2.5 mA/piece; and the treatment temperature is 0-40° C.

Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.

Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract: A solid-state imaging element has problems of occurrence of dark current due to influences of an interface state at an interface between a semiconductor and an insulating film, e.g., between silicon and silicon oxide, and of charges generated in a device manufacturing process, which leads to signal noise, thereby degrading the function of a device, specifically, the imaging quality. The outline of the invention in the present application relates to a manufacturing method of a semiconductor integrated circuit device with a surface-irradiation type image sensor, which includes irradiating a main surface of a semiconductor wafer with photodiodes formed therein, with far-ultraviolet ray after forming a lowermost wiring layer of a multi-layer wiring and before forming a color filter layer, and then applying a heat treatment to the wafer.

Abstract: A semiconductor device includes a wiring substrate including a first electrode in which a cross-sectional shape is an inverted trapezoidal shape, a semiconductor chip including a second electrode in which a cross-sectional shape is an inverted trapezoidal shape, a metal bonding material bonding a tip end of the first electrode and a tip end of the second electrode which face each other, and an underfill resin filled between the wiring substrate and the semiconductor chip, the underfill resin covering a side face of each of the first electrode and the second electrode and a side face of the metal bonding material.

Abstract: In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies.

Abstract: A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Abstract: A method of fabricating a semiconductor device includes forming line patterns over a first region of an etch target layer and a pre-pad pattern over second and third regions of the etch target layer; forming pillars over the line patterns and a sacrificial pad pattern over the pre-pad pattern; forming first spacers over sidewalls of the pillars such that the first spacers contact one another and form first pre-openings therebetween; removing the pillars to form second pre-openings; cutting the line patterns through the first and second pre-openings, and forming cut patterns; etching the pre-pad pattern using the sacrificial pad pattern as an etch mask, and forming a pad pattern; and etching the etch target layer using the cut patterns and the pad pattern as an etch mask, to define first patterns and a second pattern over the first region and the second region, respectively.

Abstract: This application discloses a light-emitting diode comprising a first semiconductor layer, an active layer on the first semiconductor layer, a second semiconductor layer on the active layer, and a semiconductor contact layer on the second semiconductor layer. The second semiconductor layer comprises a first sub-layer and a second sub-layer formed above the first sub-layer, wherein the material of the second sub-layer comprises AlxGa1-xN (0<x<1) and the second sub-layer has a surface comprising a structure of irregularly distributed holes.

Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Abstract: A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.

Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of patterning features atop a layer of a semiconductor device, and implanting ions into a sidewall surface of the set of patterning features. The method includes implanting ions at an angle nonparallel with the sidewall surface, for example, approximately 60° to a plane normal to the sidewall surface. The method further includes etching the semiconductor device after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation as a pretreatment prior to etching, photoresist roughness is minimized, and sidewall striation and etch-induced line edge roughness is reduced. Approaches herein may also improve etch selectivity with respect to underlying layers disposed under the photoresist, as well as improved photoresist profiles.