Abstract: A packaging method for an organic light emitting display panel, an organic light emitting display panel and a display device are disclosed. The packaging method includes: forming a water/oxygen blocking layer that covers a whole base substrate on the base substrate with an organic light emitting device and a peripheral bonding region formed thereon, etching the water/oxygen blocking layer on the base substrate, so as to at least remove the water/oxygen blocking layer on a connection terminal within the bonding region, and to retain the water/oxygen blocking layer on the organic light emitting device. With the packaging method, an organic light emitting display panel with a narrow frame can be realized.

Abstract: According to embodiments of the present invention, a semiconductor substrate is formed on at least a portion of a surface of a semiconductor substrate. The emitting layer is excited for a first predetermined time period. A first luminescent intensity value of the emitting layer is determined. In response to exposing the semiconductor substrate and the emitting layer to a condition for a second predetermined time period, a second luminescent intensity value of the emitting layer is determined. A thermal profile of at least the portion of the surface of the semiconductor substrate is determined utilizing the first luminescent intensity value and the second luminescent intensity value of the emitting layer. The thermal profile at least reflects information about one or more of the condition and the semiconductor substrate subsequent to exposure to the condition.

Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Abstract: Plasma atomic layer deposition (ALD) is optimized through modulation of the gas residence time during an excited species phase, wherein activated reactant is supplied such as from a plasma. Reduced residence time increases the quality of the deposited layer, such as reducing wet etch rates, increasing index of refraction and/or reducing impurities in the layer. For example, dielectric layers, particularly silicon nitride films, formed from such optimized plasma ALD processes have low levels of impurities remaining from the silicon precursor.

Abstract: A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.

Abstract: A power module includes a substrate DMB (Direct Metal Bonded). A novel bridging DMB is surface mounted to the substrate DMB along with power semiconductor device dice. The top metal layer of the bridging DMB has one or more islands to which bonding wires can connect. In one example, an electrical path extends from a module terminal, through a first bonding wire and to a first location on a strip-shaped island, through the island to a second location, and from the second location and through a second bonding wire. The strip-shaped island of the bridging DMB serves as a section of the overall electrical path. Another bonding wire of a separate electrical path passes transversely over the strip-shaped island without any wire crossing any other wire. Use of the bridging DMB promotes bonding wire mechanical strength as well as heat sinking from bonding wires down to the substrate DMB.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.

Abstract: Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

Abstract: A semiconductor device includes a wiring substrate, a first semiconductor chip flip-chip connected to the wiring substrate, a first underfill resin filled between the wiring substrate and the first semiconductor chip, the first underfill resin including a pedestal portion arranged in a periphery of the first semiconductor chip, a second semiconductor chip flip-chip connected to the first semiconductor chip, and being larger in area than the first semiconductor chip, and a second underfill resin filled between the first semiconductor chip and the second semiconductor chip, the second underfill resin covering an upper face of the pedestal portion of the first underfill resin and a side face of the second semiconductor chip.

Abstract: A thin film transistor (TFT) substrate includes a substrate which is a flexible substrate, and a TFT structure disposed on the substrate and including a gate layer, a gate insulator layer, a first channel island and a second channel island. The gate layer is disposed on the substrate and including a first gate electrode and a second gate electrode electrically connected to each other. The first and second gate electrodes are parts of the same TFT structure. The gate insulator layer covers the first and second gate electrodes. The first and second channel islands are disposed on the gate insulator layer and respectively correspond to the first and second gate electrodes. The source and drain layer is disposed on the gate insulator layer and next to the first and second channel islands, wherein the source and drain layer partially covers top surfaces of the first and second channel islands.

Abstract: An etching method using a bevel etching apparatus is provided. The bevel etching apparatus is configured to etch a substrate by emitting a laser beam and includes a laser generator and a power meter configured to measure the laser beam output from the laser generator. In the method, the power meter is irradiated with the laser beam for a predetermined period of time before etching the substrate by irradiating the substrate with the laser beam. An output value of the laser beam is measured by the power meter. It is determined whether the measured output value of the laser beam is in a range of predetermined thresholds with respect to an output setting value of the laser beam output from the laser generator.

Abstract: Disclosed is a method for manufacturing a solar cell module (10), said method being provided with: a first step for a first step for manufacturing a laminated body by sequentially stacking and thermocompression-bonding a solar cell (11), sealing material (14), first protection member (12) and second protection member (13); and a second step, which is a step of heating the solar cell (11) of the laminated body, and in which the sealing material (14) is indirectly heated due to a temperature increase of the solar cell (11).

Abstract: In a wafer processing method, a protective film is formed by applying a liquid resin to the front side of a wafer. A protective tape is adhered to a surface of the protective film. A modified layer is formed by applying a laser beam having such a wavelength as to be transmitted through the wafer along each of division lines, with a focal point positioned inside the wafer. The modified layer is formed inside the wafer along each of the division lines. The back side of the wafer is ground while supplying grinding water to thin the wafer to a predetermined thickness and to crack the wafer along the division lines using the modified layers as crack starting points so as to divide the wafer into individual device chips, after the protective film is formed, the protective tape is adhered, and the modified layer is formed.

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: An apparatus for forming a thin film on a substrate in a reaction container by alternately supplying a raw material gas and a reaction gas into the reaction container under a vacuum atmosphere is provided. The apparatus includes: a raw material gas supply unit installed in an end portion of a supply path of the raw material gas; a pressure adjusting valve installed in an vacuum exhaust path; a pressure regulating valve and an opening and closing valve which are respectively installed in a bypass path detouring the pressure adjusting valve; a tank installed in the middle of the supply path of the raw material gas; a flow rate adjusting valve installed in a downstream side of the tank; and a control unit configured to control the opening and closing valve to be opened when the raw material gas stored in the tank is supplied into the reaction container.

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.

Abstract: A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.

Abstract: An electroluminescent element includes a first transparent electrode, a second transparent electrode, a light emitting layer sandwiched between the first transparent electrode and the second transparent electrode, a first transparent member formed on a surface of the first transparent electrode opposite to the light emitting layer, and a second transparent member formed on a surface of the second transparent electrode opposite to the light emitting layer, wherein refractive indices of the first transparent electrode and the second transparent electrode are selected such that as seen from the light emitting layer, a reflectance of an interface between the light emitting layer and the first transparent electrode becomes higher than a reflectance of an interface between the light emitting layer and the second transparent electrode, and wherein a refractive index of the first transparent member is set to be higher than a refractive index of the second transparent member.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.