Abstract: A method for manufacturing an array substrate, an array substrate and a display panel are provided herein. The method for manufacturing the array substrate includes: forming an inorganic layer on a base substrate; defining a preset region in a marginal region of the base substrate, and removing the inorganic layer in the preset region; and cutting the base substrate or the base substrate together with one or more layers on the base substrate in the preset region.

Abstract: The present disclosure provides a stretchable display device, comprising: a lower substrate made of a stretchable insulating material and having an active area and a non-active area adjacent to the active area; a plurality of individual substrates spaced apart from each other and disposed in the active area of the lower substrate; pixels disposed on the plurality of individual substrates respectively; and a plurality of connecting lines disposed between the plurality of individual substrates on the lower substrate, and electrically connecting corresponding pads disposed within the plurality of individual substrates respectively. The modulus of the plurality of individual substrates is higher than the lower substrate.

Abstract: This organic EL display device (100) has multiple pixels, and comprises: an element substrate (1) which has a substrate and multiple organic EL elements supported on the substrate and arranged in each of the multiple pixels; and a thin-film sealing structure (10) covering the multiple pixels. The thin-film sealing structure has a first inorganic barrier layer (12) and an organic barrier layer (14) contacting the upper surface or the lower surface of the first inorganic barrier layer. The element substrate further has a bank layer (33) defining each of the multiple pixels and multiple spacers (31) arranged in the gaps between the pixels, and the multiple spacers (31) are covered by the bank layer (33).

Abstract: A package includes a plurality of dies, a wall structure, an encapsulant, and a redistribution structure. The wall structure surrounds at least one of the dies. The encapsulant includes a first portion, a second portion, and a third portion. The first portion is encircled by the wall structure. The second portion encircles the wall structure. The third portion connects the first portion and the second portion. The redistribution structure is disposed on the encapsulant and is electrically connected to the dies and the wall structure.

Abstract: A method of forming an electrically insulating barrier between a source contact and a drain contact of a transistor device including an electrically insulating layer disposed atop a semi-conductive layer, and an electrically conductive layer disposed atop the electrically insulating layer, the source contact and the drain contact extending from the electrically conductive layer through the electrically insulating layer to the semi-conductive layer, the method including disposing a hardmask layer atop the electrically conductive layer, disposing a photoresist layer atop the hardmask layer, performing a photolithography process to form a trench in the hardmask layer to expose an underlying portion of the electrically conductive layer spanning between the source contact and the drain contact, and performing an ion implantation process, wherein an ion beam formed of ionized oxygen atoms is directed into the trench to oxidize the exposed portion of the electrically conductive layer.

Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.

Abstract: A semiconductor device includes a fin-type pattern on a substrate, a first gate structure being on the fin-type pattern and including first gate spacers and a first gate insulating layer extending along sidewalls of the first gate spacers, a second gate structure being on the fin-type pattern and including second gate spacers and a second gate insulating layer extending along sidewalk of the second gate spacers, a pair of dummy spacers between the first gate structure and the second gate structure, a separation trench being between the pair of dummy spacers and having sidewalls defined by the pair of dummy spacers and the fin-type pattern, a device isolation layer in a portion of the separation trench, and a connection conductive pattern being on the device isolating layer and in the separation trench and contacting the pair of dummy spacers.

Abstract: A light-emitting device includes: a first electrode; a second electrode; and an organic layer that is provided between the first electrode and the second electrode and is formed by stacking a first light-emitting layer and a second light-emitting layer in order from the first electrode side, in which light emitted from the organic layer is reflected by an interface between the first light-emitting layer and the first electrode, passes through the second electrode, and is emitted to the outside of the light-emitting device, a first light-transmitting layer, a second light-transmitting layer, and a third light-transmitting layer are provided on a side of the second light-emitting layer opposite to the first light-emitting layer in order from the second light-emitting layer side, and predetermined conditions are satisfied.

Abstract: An array substrate is provided. The array substrate includes a substrate, a light-shielding layer formed on the substrate, a buffer layer formed on the light-shielding layer, a semiconductor layer formed on the buffer layer, a protection layer formed on the semiconductor layer, an insulating layer formed on the protection layer, and an interlayer dielectric layer formed on the protection layer. The substrate includes a source layer, a drain layer and a gate layer disposed thereon. The source layer and the drain layer are formed on the interlayer dielectric layer. The source layer and the drain layer are separately connected to conductor portions on two ends of the semiconductor layer. The insulating layer is disposed between the gate layer and the semiconductor layer. The interlayer dielectric layer is disposed to cover the gate layer and the protection layer. The insulating layer is disposed to cover the semiconductor layer.

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

Abstract: A semiconductor device includes a plurality of nano sheet stacks disposed above a substrate. Each nanosheet stack has a first nanosheet and a first sacrificial layer, the first nanosheet and the first sacrificial layer each include a first end and a second end. The first end and the second end of the first sacrificial layer are recessed from the first and second ends of the first nanosheet. Each nanosheet stack has a bottom sacrificial layer formed on top of the substrate. The bottom sacrificial layer has a first end and a second end, which are recessed from the first and second ends of the first nanosheet. The semiconductor also has a source or drain (S/D) structures formed in contact with the first end and the second end of the first nanosheet. The S/D structures are isolated from the substrate by the bottom sacrificial layer.

Abstract: An optical unit includes an optical module that includes a light emitting element array in which a plurality of light emitting elements are arranged, a lens array disposed facing the light emitting element array on an optical path of light emitted from the plurality of light emitting elements, and a fixing part configured to fix the light emitting element array to the lens array. The optical unit also includes a member configured to have a larger coefficient of thermal expansion than a coefficient of thermal expansion of the light emitting element array and a fastening part configured to fasten the optical module on a surface of the member. The fastening part is configured to fasten the optical module so as to enable expanding and contracting in a plane parallel to the surface of the member.

Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.

Abstract: A light emitting device includes a first light transmissive supportive substrate having a first light transmissive insulator and a conductive circuitry layer provided on a surface of the first light transmissive insulator, a second light transmissive supportive substrate having a second light transmissive insulator and disposed in such a way that a surface of the second light transmissive insulator faces the conductive circuitry layer and so as to have a predetermined gap from the first light transmissive supportive substrate, a light emitting diode having a main body, and first and second electrodes provided on a surface of the main body and electrically connected to the conductive circuitry layer via a conductive bump, and laid out between the first and second light transmissive supportive substrates, and a third light transmissive insulator embedded in a space between the first light transmissive supportive substrate and the second light transmissive supportive substrate.

Abstract: An electrical device includes a first terminal structured to electrically connect to a power source; a second terminal structured to electrically connect to a load; a voltage sensor electrically connected to a point between the first and second terminals and being structured to sense a voltage at the point between the first and second terminals; a switch electrically connected between the first terminal and the second terminal; and a control unit structured to detect a power quality event in the power flowing between the first and second terminals based on the sensed voltage and to control a state of the switch based on the detected power quality event.

Abstract: This planar light source device has a pair of substrates, a pair of irradiation plates disposed between the pair of substrates, and a plurality of light emission devices disposed on one or both of the pair of substrates. In a cross-section of the light emission devices in a direction perpendicular to the irradiation plates through an optical axis, the luminosity of light emitted in a 7.0° direction when 0° is the optical axis direction and the luminosity of light emitted in a (tan?1(t/L))° (where t represents the gap between the irradiation plates, and L represents the gap, in a direction along the pair of irradiation plates, from the surface of a light emission device disposed on one of the substrates to an end part of the other-substrate-side irradiation plate) direction or a (tan?1(t/2L))° direction satisfy a prescribed relationship.

Abstract: An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

Abstract: A method of forming a wafer stack includes providing a sub-stack comprising a first wafer and a second wafer. The sub-stack includes a first thermally-curable adhesive at an interface between the upper surface of the first wafer and the lower surface of the second wafer. A third wafer is placed on the upper surface of the second wafer. A second thermally-curable adhesive is present at an interface between the upper surface of the second wafer and the lower surface of the third wafer. Ultra-violet (UV) radiation is provided in a direction of the upper surface of the third wafer to cure a UV-curable adhesive in openings in the second wafer and in contact with portions of the third wafer so as to bond the third wafer to the sub-stack at discrete locations. Subsequently, the third wafer and the sub-stack are heated so to cure the first and second thermally-curable adhesives.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.