Abstract: A light-emitting device has enhanced light output by employing a reflective optical cavity along the bank structure to improve light extraction. The light-emitting device includes a bank structure; an emissive cavity disposed within the bank structure; a filler material layer disposed within the bank structure and on a light-emitting side of the emissive cavity; and a reflective optical cavity disposed along an inner surface of the bank structure facing the filler material layer. The reflective optical cavity is configured to out-couple light that is internally reflected by an emitting side surface of the filler material layer and is incident on the reflective optical cavity. The reflective optical cavity incudes a first conductive layer and a second conductive layer that are separated by a non-conductive dielectric layer.

Abstract: The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device includes a semiconductor substrate, a semiconductor fin and a filled trench. The semiconductor fin extends upwards from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first sigma portion, a second sigma portion and a middle portion. The first sigma portion is partially filled by a semiconductor buffer region, and an unfilled part of the first sigma portion is filled by a doped semiconductor region grown on the semiconductor buffer region. The second sigma portion is filled by the semiconductor buffer region. The middle portion connects the first sigma portion to the second sigma portion, and the middle portion is filled by the semiconductor buffer region.

Abstract: A MOSFET includes a substrate, a trench, a bottom oxide, a shield poly, two gate polys and an inter-poly oxide. The trench is formed on the substrate. The bottom oxide is formed on the trench. The shield poly is formed on the trench, and a part of the bottom oxide is separated by the shield poly. The two gate polys are formed on the bottom oxide. The inter-poly oxide is formed between the two gate polys. The shield poly is staggered from at least one of the two gate polys in a horizontal direction and a vertical direction. Therefore, the capacitance between a source electrode and a gate electrode is effectively reduced, and the delay time during switching is shorten and the energy loss is reduced at the same time.

Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

Abstract: A display apparatus including a panel substrate including a TFT drive circuit for active matrix driving, a plurality of light emitting diodes, and an anisotropic conductive film electrically connecting the light emitting diodes to the panel substrate, in which the anisotropic conductive film includes an adhesive organic insulation material and conductive particles dispersed in the adhesive organic insulation material.

Abstract: An imaging device according to one aspect of the present disclosure includes: a semiconductor substrate; and pixels. Each of the pixels includes: a photoelectric converter that converts incident light into electric charge; a diffusion region provided in the semiconductor substrate and electrically connected to the photoelectric converter; a first transistor including a gate, and the diffusion region as one of a source and a drain; and a plug that is directly connected to the diffusion region, is electrically connected to the photoelectric converter, and includes a semiconductor. The height of the plug and the height of the gate from the surface of the semiconductor substrate are equal to each other.

Abstract: A light emitting diode apparatus including a substrate, a plurality of light emitting diodes regularly arranged on the substrate and configured to emit ultraviolet (UV) light, the light emitting diodes including first, second, and third sub-light emitting diodes, a plurality of phosphor layers disposed on the light emitting diodes and to convert the wavelength of light emitted from the light emitting diodes, the phosphor layers including first, second, and third phosphor layers disposed on the first, second, and third sub-light emitting diodes, respectively, and a control unit configured to supply power to the light emitting diodes, in which the phosphor layers are spaced apart from each other by a blocking region, and the control unit is configured to cause at least a portion of the light emitting diodes to emit light.

Abstract: Provided are an organic light-emitting diode display panel and a manufacturing method thereof, and a display device, in the field of display technology. The OLED display panel includes: a base substrate and plurality of light-emitting units. Each light-emitting unit includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, and a ratio of areas of light-emitting layers in the plurality of light-emitting units is within a threshold range.

Abstract: Discussed is an electroluminescent display device, wherein a first electrode of a first sub pixel includes a first lower electrode and a first upper electrode, a first electrode of a second sub pixel includes a second lower electrode and a second upper electrode, a first electrode of a third sub pixel includes a third lower electrode and a third upper electrode, a distance between the first lower electrode and the first upper electrode, a distance between the second lower electrode and the second upper electrode, and a distance between the third lower electrode and the third upper electrode are different from one another, the third upper electrode includes a third lower layer and a third upper layer, and the third lower layer is formed in the same pattern as that of the third lower electrode in an upper surface of the third lower electrode.

Abstract: Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a conductive region made of silicon, germanium or a combination thereof. The semiconductor device structure also includes an insulating layer over the semiconductor substrate and a fill metal material layer in the insulating layer. In addition, the semiconductor device structure includes a nitrogen-containing metal silicide or germanide layer between the conductive region and the fill metal material layers.

Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate; a drain disposed in the substrate; a drain contact disposed in the drain; a source disposed in the substrate; a source contact disposed in the source; a gate structure with a bottom disposed in the substrate between the drain and the source; a channel disposed at the bottom of the gate structure connecting the drain and the source; a drain stressor disposed in the drain between the gate structure and the drain contact; a drain strained silicon layer disposed in the substrate surrounding the drain stressor connected to the channel; a source stressor disposed in the source between the source contact and the gate structure; and a source strained silicon layer disposed in the substrate surrounding the source stressor connected to the channel.

Abstract: Example sensor apparatus for microfluidic devices and related methods are disclosed. In examples disclosed herein, a method of fabricating a sensor apparatus for a microfluidic device includes etching a portion of an intermediate layer to form a sensor chamber in a substrate assembly, where the substrate assembly has a base layer and the intermediate layer, and where the base layer comprises a first material and the intermediate layer comprises a second material different than the first material. The method includes forming a first electrode and a second electrode in the sensor chamber. The method also includes forming a fluidic transport channel in fluid communication with the sensor chamber, where the fluidic transport channel comprises a third material different than the first material and the second material.

Abstract: A method of manufacturing an OLED device includes: preparing a substrate on which a first conductive layer and a pixel defining film defining a plurality of pixels and exposing the first conductive layer for each of the plurality of pixels; disposing a photoresist pattern on the pixel defining film, the photoresist pattern comprising an opening exposing a first pixel of the plurality of pixels; disposing a first material layer onto an entire surface of the substrate to simultaneously dispose an organic light-emitting layer and a first deposition layer; disposing a second material layer onto the entire surface of the substrate to simultaneously dispose a second conductive layer and a second deposition layer; disposing a third material layer onto the entire surface of the substrate to simultaneously dispose a protection layer and a third deposition layer; and removing the photoresist pattern and the first, second, and third deposition layers.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.