Abstract: A method of forming fine interconnection includes: forming spacers on a first and second hard mask layer on a dielectric layer; forming a first via hole through the first hard mask layer, the second hard mask layer, and the dielectric layer; oxidizing a sidewall of the first hard mask layer that surrounding the via hole; forming a second via hole in the second hard mask layer; forming a mask to cover the first hard mask layer in the second via hole; forming a line trench in a portion of the second hard mask layer exposed by the spacers and the mask, and in the first hard mask layer and the dielectric layer that are below the portion of the second hard mask layer; and forming a conductive material in the line trench and the first via hole.

Abstract: A dielectric powder includes a core-shell structure including a core region formed in an inner portion thereof and a shell region covering the core region. The core region includes barium titanate (BaTiO3) doped with a metal oxide, and the shell region is formed of a ferroelectric material.

Abstract: A method and an apparatus are provided. The apparatus includes a three-dimensional semiconductor structure having a spherical array of fixed-position optoelectronic devices arranged over a relaxed elastomer by a controlled unbuckling process that orients the fixed-position optoelectronic devices to face in different directions in the spherical array to communicate in the different directions without motion of the apparatus and the fixed-position optoelectronic devices of the apparatus.

Abstract: A package structure is provided. The package structure includes a leadframe including a plurality of connection portions; a device including a substrate, an active layer disposed on the substrate and a plurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the connection portions of the leadframe; a conductive unit having a first side and a second side, wherein the first side of the conductive unit connects to the substrate of the device and the conductive unit connects to at least one of the connection portions of the leadframe; and an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit is exposed from the encapsulation material.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

Abstract: A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure.

Abstract: An OLED display substrate, a manufacturing method thereof, and a display device are provided. The OLED display substrate includes a reflective cathode layer, an organic light-emitting layer, a transparent anode layer and a high reflection layer sequentially arranged on a substrate, and the high reflection layer has reflectivity greater than a threshold.

Abstract: The wafer-level manufacturing method makes possible to manufacture ultrathin optical devices such as opto-electronic modules. A clear encapsulation is applied to an initial wafer including active optical components and a wafer-size substrate. Thereon, a photostructurable spectral filter layer is produced which defines apertures. Then, trenches are produced which extend through the clear encapsulation and establish sidewalls of intermediate products. Then, an opaque encapsulation is applied to the intermediate products, thus filling the trenches and producing aperture stops. Cutting through the opaque encapsulation material present in the trenches, singulated optical modules are produced, wherein side walls of the intermediate products are covered by the opaque encapsulation material. The wafer-size substrate can be attached to a rigid carrier wafer during most process steps.

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

Abstract: A method of manufacturing a magnetoresistive device may include forming a first ferromagnetic region, forming an intermediate region on or above the first ferromagnetic region. The intermediate region may be formed of a dielectric material and include nitrogen. The method may also include forming a second ferromagnetic region on or above the intermediate region.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: A bonded wafer including an ion implantation step using a batch processing ion implanter, wherein the ion implantation step is performed by irradiating a bond wafer with a light element ion beam without forming an insulator film on the bond wafer surface or through an insulator film having a thickness of 50 nm or less formed on the bond wafer surface at an implantation angle inclined from a crystal axis of the bond wafer; and the bond wafer surface is irradiated with the center of the light element ion beam shining at a position on the bond wafer surface shifted from the center of the bond wafer parallel to the center of a rotor by a predetermined amount providing a bonded wafer to prevent degradation of the radial uniformity of ion implantation depth and manufacture a bonded wafer with excellent radial uniformity of thickness of a thin film after delamination.

Abstract: A display device is provided, which includes a first substrate, a first subpixel and a second subpixel. The first subpixel is disposed on the first substrate and the second subpixel is disposed adjacent to the first subpixel. The first subpixel and the second subpixel are spaced apart from each other by a pitch. At least one of the first subpixel and the second subpixel includes a light-emitting unit and a light conversion layer disposed on the light-emitting unit. The first subpixel includes an active layer having a first length along a direction that is perpendicular to a normal direction of the first substrate. The light conversion layer has a second length along the direction that is perpendicular to the normal direction of the first substrate. The first length (A), the second length (B) and the pitch (Sp) conform to the following formula: A+1 micrometers<B<Sp?1 micrometers.

Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.

Abstract: A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base material with an interface layer film of silicon dioxide sandwiched therebetween, and a metal gate electrode containing fluorine is further formed thereon. A heat treatment apparatus radiates flash light from a flash lamp to the semiconductor wafer in an atmosphere containing hydrogen to carry out heating treatment for an extremely short period of time of 100 milliseconds or less. As a result, diffusion of nitrogen contained in the metal gate electrode is inhibited, at the same time, only the fluorine is diffused from the high-dielectric-constant gate insulating film to an interface between the interface layer film and the silicon base material to reduce an interface state, and reliability of the gate stack structure can be improved.

Abstract: Light emitting devices (LEDs) are described. An LED includes a light emitting semiconductor structure that includes a light emitting active layer disposed between an n-layer and a p-layer. A wavelength converting material may be disposed adjacent the light emitting semiconductor structure. The wavelength converting material includes multiple pores, at least one of which contains a second material. An absolute value of a ratio of a coefficient of thermal expansion of the second material to a coefficient of thermal expansion of the wavelength converting material is at least two in an embodiment, at least ten in another embodiment, at least 100 in another embodiment, and at least 1,000 in yet another embodiment.

Abstract: This disclosure relates to dielectric film forming compositions containing a) at least one fully imidized polyimide polymer; b) at least one metal-containing (meth)acrylates; c) at least one catalyst; and d) at least one solvent, as well as related processes and related products. The compositions can form a dielectric film that generates substantially no debris when the dielectric film is patterned by laser ablation process.

Abstract: A package structure is provided. The package structure includes a redistribution layer and a first integrated circuit chip having a first chip edge and a second integrated circuit chip having a second chip edge over the redistribution layer. The package structure also includes first bumps electrically connected to the first integrated circuit chip through the redistribution layer. In addition, the first bumps overlap the first integrated circuit chip and are arranged along a first chip edge of the first integrated circuit chip. The package structure further includes second bumps electrically connected to the first integrated circuit chip through the redistribution layer without overlapping the first integrated circuit chip and the second integrated circuit chip. In addition, none of the second bumps is arranged between the first chip edge and the second chip edge.