Patents by Inventor A. Ashok Kumar

A. Ashok Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100082987
    Abstract: A transparent trust validation of an unknown platform can be performed by communicationally coupling it to a trusted device, such as a portable peripheral device carried by a user, or one or more remote computing devices. Information from the unknown platform can be obtained by boot code copied to it from the trusted device and such information can be validated by the trusted device. The trusted device can then provide an encrypted version of decryption key to the boot code which can request the Trusted Platform Module (TPM) of the unknown platform to decrypt and return the decryption key. If the information originally obtained from the unknown platform and validated by the trusted device was authentic, the TPM will be able to provide the decryption key to the boot code, enabling it to decrypt an encrypted volume comprising applications, operating systems or other components.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Stefan Thom, Shon Eizenhoefer, Erik Holt, Yash Ashok Kumar Gandhi
  • Publication number: 20100081847
    Abstract: Disclosed herein is a novel process for preparation of atovaquone. The process includes reacting 1,4-naphthoquinone with trans-4-(4-chlorophenyl) cyclohexane carboxylic acid followed by halogenation to obtain a dihalo-compound. Further, dehydrohalogenation of the dihalo-compound produces a monohalogeno-compound which under goes hydrolysis to produce atovaquone. The invention also discloses atovaquone in a substantially pure and well defined polymorphic form designated as “Form IPCA-ATO,” and the preparation thereof.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 1, 2010
    Inventors: Ashok Kumar, Suneel Yeshwant Dike, Pramilkumar Mathur, Nellithanath Thankachen Byju, Brajesh Sharma, Swapnil Shreekant Kore, Vitthal Suryabhan Buchude, Dharmendra Singh
  • Patent number: 7687335
    Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 30, 2010
    Assignee: SuVolta, Inc.
    Inventor: Ashok Kumar Kapoor
  • Patent number: 7683433
    Abstract: An apparatus and method of manufacture for metal-oxide semiconductor (MOS) transistors is disclosed. Devices in accordance with the invention are operable at voltages below 2V. The devices are area efficient, have improved drive strength, and have reduced leakage current. A dynamic threshold voltage control scheme comprised of a forward biased diode in parallel with a capacitor is used, implemented without changing the existing MOS technology process. This scheme controls the threshold voltage of each transistor. In the OFF state, the magnitude of the threshold voltage of the transistor increases, keeping the transistor leakage to a minimum. In the ON state, the magnitude of the threshold voltage decreases, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS. The use of reverse biasing of the well, in conjunction with the above construct to further decrease leakage in a MOS transistor, is also shown.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: March 23, 2010
    Assignee: Semi Solution, LLC
    Inventors: Ashok Kumar Kapoor, Robert Strain, Reuven Marko
  • Patent number: 7678413
    Abstract: A monoclinic CeTi2O6 thin film and a sol-gel process for the deposition of CeTi2O6 thin films, which has applications as passive counter electrodes in electrochromic devices, sensors and photocatalytic agent is presented. This film can be obtained by spin coating a solution, which comprises both titanium and cerium precursors on to electrically conducting or insulating glass substrates and annealing at a temperature of 600° C. for 5 min. in air. The Ce:Ti mole ratio in the deposition sol for the preparation of the film is identified in the range of 0.4:1 and 0.6:1.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 16, 2010
    Assignee: Council of Scientific & Industrial Research
    Inventors: Verma Amita, Agnihotry Suhasini Avinash, Bakhshi Ashok Kumar
  • Publication number: 20100044294
    Abstract: A spherical dialysis chamber with a heavier cap (the density of cap material is higher than that of the dialyzer) or the distribution of weight is such that it is higher weight distribution is towards the cap, so that it tilts always towards the bottom of the container containing the dialysis buffer.
    Type: Application
    Filed: August 25, 2009
    Publication date: February 25, 2010
    Inventors: Ashok Kumar Shukla, Mukta Misra Shukla, Kavita Misra Shukla
  • Publication number: 20100046312
    Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices.
    Type: Application
    Filed: November 2, 2009
    Publication date: February 25, 2010
    Inventor: Ashok Kumar KAPOOR
  • Patent number: 7665291
    Abstract: A system and method for recovering heat from dirty gaseous fuel (syngas), wherein the pressure of clean fuel gas is elevated to a pressure higher than that of the dirty syngas and then the pressurized clean fuel gas is fed to a heat recovery unit for heat exchange with the dirty syngas. Consequently, in the event of a leak in the heat recovery unit, the flow is from the clean fuel side to the dirty syngas side, thereby avoiding the possibility of contamination of the clean fuel gas.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: February 23, 2010
    Assignee: General Electric Company
    Inventors: Ashok Kumar Anand, Patrick King Wah May, Michael Jandrisevits
  • Publication number: 20100025634
    Abstract: A process for the treatment of a high-pressure hydrocarbon gas stream to make a carbon dioxide-rich product stream and a treated hydrocarbon gas product stream by contacting within a contactor the high-pressure hydrocarbon gas stream with a solvent containing aqueous ammonia and, optionally, a reaction product of a liquid ammonia-carbon dioxide-water system. A fat solvent containing precipitated solids is withdrawn from the contactor and is regenerated whereby carbon dioxide is released and the fat solvent and a lean solvent is provided for reuse as the solvent.
    Type: Application
    Filed: July 9, 2009
    Publication date: February 4, 2010
    Inventors: Jose Luis BRAVO, Ashok Kumar Rupkrishen DEWAN, Raymond Nicholas FRENCH, Amrit Lal KALRA, Pervaiz NASIR, Jiri Peter Thomas VAN STRAELEN
  • Patent number: 7651905
    Abstract: An apparatus and method for the reduction of gate leakage in deep sub-micron metal oxide semiconductor (MOS) transistors, especially useful for those used in a cross coupled static random access memory (SRAM) cell, is disclosed. In accordance with the invention, the active element of the SRAM cell is used to reduce the voltage on the gate of its transistor without impacting the switching speed of the circuit. Because the load on the output of the inverter is fixed, a reduction in the gate current is optimized to minimize the impact on the switching waveform of the memory cell. An active element formed by two materials with different Fermi potentials is used as a rectifying junction or diode. The rectifying junction also has a large parallel leakage path, which allows a finite current flow when a signal of opposite polarity is applied across this device.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: January 26, 2010
    Assignee: Semi Solutions, LLC
    Inventor: Ashok Kumar Kapoor
  • Publication number: 20100006803
    Abstract: A method of treating a high-pressure hydrocarbon stream, such as natural or synthetic gas, contaminated with a high concentration of carbon dioxide, by contacting the contaminated high-pressure hydrocarbon stream with a chilled aqueous ammonia solution in an absorber at high pressure to produce a treated gas stream having a substantially reduced carbon dioxide content and a carbon dioxide-rich ammonia solution. The carbon dioxide-rich ammonia solution is regenerated by stripping, thus producing a concentrated carbon dioxide stream at high pressure suitable for sequestration or other uses.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 14, 2010
    Inventors: Jose Luis Bravo, Ashok Kumar Rupkrishen Dewan, Raymond Nicholas French, Amrit Lal Kalra, Pervaiz Nasir, Jiri Peter Thomas Van Straelen
  • Patent number: 7642566
    Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 5, 2010
    Assignee: DSM Solutions, Inc.
    Inventors: Madhukar B. Vora, Ashok Kumar Kapoor
  • Patent number: 7640239
    Abstract: The invention provides methods for enterprise business visibility that transform any of marketing, e-commerce and transactional from a plurality of legacy and other databases into resource description framework (RDF) syntax. This information can be time-stamped (e.g., with expiration dates) and stored in a central data store. Answers to queries are discerned by applying genetic algorithm-based search techniques to the holographic store, with the confidence levels of those answers is based in part, for example, on the time-stamps of the triples.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: December 29, 2009
    Assignee: Metatomix, Inc.
    Inventors: Colin P. Britton, Amir Azmi, Ashok Kumar, Noah W. Kaufman, Chandra Bajpai, Robert F. Angelo, David A. Bigwood
  • Publication number: 20090318465
    Abstract: The present invention relates to a method for identifying compounds that act as insulin-sensitizers. The method can include screening of test compounds in two assays of insulin sensitivity. This method can identify lead compounds for the treatment of disorders caused by insulin resistance to glucose uptake. This invention also includes methods for treating insulin resistance and related disorders.
    Type: Application
    Filed: September 20, 2007
    Publication date: December 24, 2009
    Inventors: Rosalind Adaikalasamy Marita, Somesh Sharma, Jessy Anthony, Kelkar Aditya, Sujit Kaur Bhumra, Aditee Ghate, Kumar Venkata Subrahman Nemmani, Nabajyoti Deka, Ashok Kumar Gangopadhyay
  • Patent number: 7635494
    Abstract: This invention relates to a novel herbal composition comprising an extract of flowering and fruiting heads of the plant, Sphaeranthus indicus. The said extract of Sphaeranthus indicus contains a compound, 3a-hydroxy-5a,9-dimethyl-3-methylene-3a,4,5,5a,6,7,8,9b-octahydro-3H-naphtho[1,2-b]furan-2-one (7-Hydroxy-4,11(13)-eudesmadien-12,6-olide) (compound 1), as a bioactive marker. The invention also relates to a composition comprising 3a-hydroxy-5a,9-dimethyl-3-methylene-3a,4,5,5a,6,7,8,9b-octahydro-3H-naphtho[1,2-b]furan-2-one (compound 1) as an active ingredient. The invention also relates to methods of manufacture of the said compositions. The invention also relates to methods of administration of the said compositions to a subject in need of treatment for an inflammatory disorder. The invention also relates to tumor necrosis factor- (TNF-?) and interleukin (IL-1, IL-6, IL-8) inhibitory activity of the said compositions.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 22, 2009
    Assignee: Piramal Life Sciences Limited
    Inventors: Vijay Chauhan, Ashish Suthar, Dhananjay Sapre, Swati Bal-Tembe, Ashok Kumar Gangopadhyay, Asha Kulkarni-Almeida, Sapna Hasit Parikh, Ravindra Dattatraya Gupte, Nilesh Madhukar Dagia, Somesh Sharma, Shruta Sudheer Dadarkar, Mahesh Gundaji Jadhav, Aditi Amol Tannu
  • Patent number: 7633101
    Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: December 15, 2009
    Assignee: DSM Solutions, Inc.
    Inventors: Madhukar B. Vora, Ashok Kumar Kapoor
  • Patent number: 7629465
    Abstract: An improved process for the manufacture of Clopidogrel starting from 2-(2-thienyl) ethylamine, which eliminates the isolation of an unstable intermediate like 2-(2-thienyl) ethyl formimine by subjecting it to a one pot cyclization to get 4, 5, 6, 7-tetrahydrothieno (3,2-c) pyridine of Formula II and further reacting with halo-compound of Formula III (where X is Cl or Br) at 20 to 90° C. temperature characterized in a solvent like water and/or dichloroethane in presence of organic or inorganic bases is disclosed herein. This invention further discloses a process for resolution of racemic Clopidogrel into its optical antipodes and converting the dextroclopidogrel base into its known polymorphs namely ‘Form I’ or ‘Form II’ in solvents selected from methyl propyl ketone, methyl isopropyl ketone, diethyl ketone or their mixture thereof, mixture of ethyl acetate and methyl propyl ketone, mixture of ethyl acetate and methyl isopropyl ketone, or mixture of ethyl acetate and diethyl ketone or ethyl acetate.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: December 8, 2009
    Assignee: IPCA Laboratories Ltd.
    Inventors: Ashok Kumar, Ketan Dhansukhlal Vyas, Sanjay Govind Barve, Priti Jayesh Bhayani, Sanjay Nandavadekar, Chirag Hasmukh Shah, Sandeep Madhavrao Burudkar, Lavkesh Dayashankar Kushwaha
  • Publication number: 20090293889
    Abstract: A consumable compressed tobacco product adapted to dissolve in an oral cavity. The compressed tobacco product is formed from a composition that includes at least one tobacco component, at least one flavorant, at least one filler-binder, at least one lubricant, at least one desiccant and at least one glidant. The compressed tobacco products are adapted to dissolve and provide tobacco satisfaction. A method of making a dissolvable compressed tobacco product is also provided.
    Type: Application
    Filed: November 26, 2008
    Publication date: December 3, 2009
    Applicant: PHILIP MORRIS USA INC.
    Inventors: Ashok Kumar, Carolina Marun, Gregory J. Griscik, David R. Golob, Jon Regrut, Suresh Shenoy, William R. Sweeney, Manuel Marquez-Sanchez
  • Publication number: 20090284013
    Abstract: A power generation system capable of eliminating NO, components in the exhaust gas by using a 3-way catalyst, comprising a gas compressor to increase the pressure of ambient air fed to the system; a combustor capable of oxidizing a mixture of fuel and compressed air to generate an expanded, high temperature exhaust gas; a gas turbine engine that uses the force of the high temperature gas; an exhaust gas recycle (EGR) stream back to the combustor; a 3-way catalytic reactor downstream of the gas turbine engine outlet which treats the exhaust gas stream to remove substantially all of the NOx components; a heat recovery steam generator (HRSG); an EGR compressor; and an electrical generator.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 19, 2009
    Applicant: General Electric Company
    Inventors: Ashok Kumar Anand, James Anthony West, Gilbert Otto Kraemer, Hasan Ul Karim, Sam David Draper, Jonathan Dwight Berry
  • Publication number: 20090286499
    Abstract: A multimode receiver/down converter architecture for use with narrow channel bandwidth and channel bandwidth system signals is described. Interfering signals for a selected narrowband channel are attenuated using a method that reduces the dynamic range of the signal for further processing. The proposed method can be used with a receiver architecture, such as Direct-Conversion, low IF, Super heterodyne, and the like. The downconverted signal is split into two paths. One signal path is delayed and subtracted from the signal from the other path. By controlling the delay value, the interference signals at a given offset are attenuated. Based on the chosen architecture, the desired signal is placed so that the signal undergoes minimal distortion.
    Type: Application
    Filed: May 20, 2009
    Publication date: November 19, 2009
    Inventors: Ashok Kumar MARATH, Naveen Altaf Ahmed SYED