Patents by Inventor A. Ashok Kumar

A. Ashok Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Oxide isolated metal silicon-gate JFET
    Publication number: 20080014687
    Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.
    Type: Application
    Filed: July 11, 2006
    Publication date: January 17, 2008
    Inventors: Madhukar B. Vora, Ashok Kumar Kapoor
  • One-Pot Process for the Preparation of Antiemetic Agent, 1,2,3,9-Tetrahydro-9-Methyl-3[(2-Methyl)-1H-Imidazole-1-Yl)Methyl]-4H-Carbazol-4-O
    Publication number: 20080009635
    Abstract: A one-pot industrial process for preparing 1,2,3,9-tetrahydro-9-methyl-3-[(2-methyl-1H-imidazole-1-yl)methyl]-4H-carbazol-4-one of Formula-(I) from 1,2,3,9-tetrahydro-9-methyl-4H-carbazol-4-one of Formula-(IV) involves reaction of Formula (IV) with HNR1R2 salt and paraformaldehyde, where R1,R2 are independently alkyl groups or together forms a cyclic alkyl group, in a solvent system of acetic acid and hydrocarbon solvent to form a crude mixture of intermediate compounds of Formula (III) and (VIII), which is converted to ondansetron (Formula (I)) without isolation by reaction with 2methyimidazole in a suitable solvent system in the same pot.
    Type: Application
    Filed: October 26, 2004
    Publication date: January 10, 2008
    Inventors: Ashok Kumar, Dharmendra Singh, Atul Jadhav, Navinchandra Pandya, Shankar Panmand, Ramsingh Thakur
  • Methods and apparatus for querying a relational data store using schema-less queries
    Patent number: 7318055
    Abstract: The invention provides, in one aspect, a method of searching an RDF triples data store of the type in which the triples are maintained in accord with a first storage schema. The method includes inputting a first query specifying RDF triples that are to be identified in the data store. That first query assumes either (i) that the triples are stored in a schema-less manner (i.e., with no storage schema) or (ii) that the triples are maintained in accord with a second storage schema that differs from the first. The method further includes generating, from the first query, a second query that specifies those same RDF triples, yet, that reflects the first storage schema. That second query can be applied to the RDF triples data store in order to identify and/or retrieve the desired data.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: January 8, 2008
    Assignee: Metatomix, Inc.
    Inventors: Colin P. Britton, Ashok Kumar, David A. Bigwood, Anthony J. DeFusco, Howard Greenblatt
  • Semiconductor device with circuits formed with essentially uniform pattern density
    Publication number: 20080001233
    Abstract: A semiconductor device can include a first circuit section having at least one transistor coupled to at least three conductive lines formed from a conductive layer. No more than one of the at least one of the three conductive lines forms a control terminal of the at least one transistor. In addition, a second circuit section includes at least two transistors. Each such transistor can have a control terminal formed by a conductive line formed from the same conductive layer. The three conductive lines of the first circuit section can have the same pitch pattern as the conductive lines of the second circuit section.
    Type: Application
    Filed: September 28, 2006
    Publication date: January 3, 2008
    Inventors: Ashok Kumar Kapoor, Richard K. Chou, Damodar R. Thummalapally
  • Silicon-on-insulator (SOI) junction field effect transistor and method of manufacture
    Publication number: 20080001183
    Abstract: A semiconductor device including complementary junction field effect transistors (JFETS) manufactured on a silicon on insulator (SOI) wafer is disclosed. A p-type JFET includes a control gate formed from n-type polysilicon and an n-type JFET includes a control gate formed from p-type polysilicon. The complementary JFETs may include four terminal JFETs having a back gate formed below a channel region. The back gate may be electrically connected to a control gate formed above a channel region via a cut region in an isolation structure. Furthermore, the complementary JFETs may be formed on strained silicon formed on a silicon germanium (SiGe) or silicon germanium carbon (SiGeC) layer, or the like.
    Type: Application
    Filed: August 22, 2006
    Publication date: January 3, 2008
    Inventor: Ashok Kumar Kapoor
  • Industrial preparation of 11-[4-{2-(2-hydroxyethoxy) ethyl}-1-piperazinyl] dibenzo [b,f]-[1,4]thiazepine
    Publication number: 20070293471
    Abstract: Disclosed herein is an industrial preparation of Quetiapine by the reaction of 11-piperazinyldibenzo[b,f][1,4]-thiazepine or its salt with 2-(2-chloroethoxy)ethanol in presence of an organic or inorganic base under neat or aqueous condition to form 11-[4-{2-(2-hydroxyethoxy)ethyl}-1-piperazinyl]dibenzo[b,f]-[1,4]thiazepine. The quetiapine free base obtained is further converted to its hemi-fumarate salt.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 20, 2007
    Inventors: Ashok Kumar, Dharmendra Singh, Swapnali Patil, Ganesh Mahale, Uttamrao Sawant, Balasaheb Jadhav, Ragneshkumar Rana
  • Self aligned gate JFET structure and method
    Publication number: 20070284628
    Abstract: A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
    Type: Application
    Filed: June 9, 2006
    Publication date: December 13, 2007
    Inventor: Ashok Kumar Kapoor
  • Scalable process and structure for JFET for small and decreasing line widths
    Publication number: 20070284626
    Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
    Type: Application
    Filed: June 12, 2006
    Publication date: December 13, 2007
    Inventors: Madhukar B. Vora, Ashok Kumar Kapoor
  • Methods and apparatus for statistical data analysis and reduction for an enterprise application
    Patent number: 7302440
    Abstract: The invention provides methods of time-wise data reduction that include the steps of inputting data from a source; summarizing that data according to one or more selected epochs in which it belongs; and generating for each such selected epoch one or more RDF triples characterizing the summarized data. The data source may be, for example, a database, a data stream or otherwise. The selected epoch may be a second, minute, hour, week, month, year, or so forth. The triples may be output in the form of RDF document objects. These can be stored, for example, in a hierarchical data store such as, for example, a WebDAV server. Triples parsed from the document objects may be maintained in a relational store that is organized, for example, according to a hashed with origin approach.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: November 27, 2007
    Assignee: Metatomix, Inc.
    Inventors: Colin P. Britton, Ashok Kumar, David Bigwood, Howard Greenblatt
  • Circuit configurations having four terminal JFET devices
    Publication number: 20070262793
    Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.
    Type: Application
    Filed: June 13, 2006
    Publication date: November 15, 2007
    Inventor: Ashok Kumar Kapoor
  • Method for manufacture of compounds related to the class of substituted sulfonyl urea anti-diabetics
    Publication number: 20070255056
    Abstract: The present invention relates to a process for preparation of sulfonyl urea compounds in high conversion rates and purity. More specifically, this invention relates to a process for manufacture of sulfonyl urea class of anti-diabetic pharmaceutical drugs in higher purity and yield. The process may effectively and economically be used to produce anti-diabetic drugs, such as glimepiride, glipizide, gliclazide, glibenclamide, glibornuride, and glisoxepide.
    Type: Application
    Filed: March 10, 2006
    Publication date: November 1, 2007
    Inventors: Ashok Kumar, Satish Soudagar, Pramil Mathur, Arpana Mathur, Dadaso Dalavi, Sanjay Gunjal, Uttamrao Sawant, Ashvini Saxena, Bimal Srivastava, Praveen Singh, Jagdish Sankla, Vijay Dhurandhare
  • Measuring mean time between software failures using customer error reporting
    Patent number: 7287191
    Abstract: A method, apparatus, and article of manufacture for measuring a mean time between program failures by maintaining a running count of program crashes per user per product version on a customer computer, and transmitting this information to a server computer when customers send error reports.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: October 23, 2007
    Assignee: Autodesk, Inc.
    Inventors: Ashok Kumar Gadangi, Joel Stephen Petersen
  • Process for manufacture of 4-amino-hydroxybutylidene-1,1-bisphosphonic acid and its salts
    Publication number: 20070149486
    Abstract: The preset invention relates to a cost effective, high yielding, reproducible method for the manufacture of alendronic acid or its salt, such as sodium alendronate, from inexpensive and readily available pyrrolidone using phosphonating agents such as PCl3 in the presence of acids such as sulphonic acids, sulphuric acid or phosphoric acid, and pharmaceutical dosage forms of alendronic acid or pharmaceutically acceptable salts thereof.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Inventors: Ashok Kumar, Suneel Dike, Avinash Nijasure, Vijaya Bhaware
  • Method, system and computer program product for positioning and synchronizing wireless communications nodes
    Patent number: 7224984
    Abstract: An asset positioning method and system (700) rapidly and accurately determine the special location of wireless nodes distributed in three-dimensional space. Furthermore, as a by-product, every node also determines the relative offset and drift of every other node's clock, so that it is possible for all nodes to carry out a precise synchronized action (708). The positioning and synchronization protocol has significant implications for a broad range of wireless networking infrastructure and applications. For instance, the rapid availability of accurate location information greatly simplifies and optimises the implementation of ad-hoc networks and sensor-based applications (716). Additionally, the synchronized node operations facilitate the development of new applications, such as phase-locked arrays, in which several low power transmitters coordinate to form a powerful group transmitter.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: May 29, 2007
    Assignee: University of Maryland, College Park
    Inventors: Ashok Kumar Agrawala, Ronald L Larsen, A. Udaya Shankar, Douglas C Szajda
  • Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
    Patent number: 7224205
    Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: May 29, 2007
    Assignee: Semi Solutions, LLC
    Inventor: Ashok Kumar Kapoor
  • Tramadol recovery process
    Publication number: 20070112074
    Abstract: A process for the resolution of isomeric tramadol mixtures comprising: providing a purification stock comprising both cis and trans tramadol; contacting the purification stock with an acid under conditions effective to form an acid salt of the cis and trans tramadol in the purification stock; and separating the cis tramadol acid salt from the trans tramadol to obtain a purified cis tramadol acid salt; and optionally converting the cis tramadol acid salt to cis tramadol or to a pharmaceutically active salt thereof.
    Type: Application
    Filed: November 13, 2006
    Publication date: May 17, 2007
    Inventors: Ashok Kumar, Suneel Dike, Satish Soudagar, Chirag Shah, Sandeep Burudkar, Prashant Gautam, Byju Thankachen, Ashvini Saxena, Manavalan Saravanan, Gunjan Pathak, Virendra Pal, Rahul Karde, Jaysingh Gehlot
  • Process for enhanced recovery of crude oil from oil wells using novel microbial consortium
    Publication number: 20070092930
    Abstract: The present invention provides a microbial consortium containing three hyperthermophilic, barophilic, acidogenic, anaerobic bacterial strains for enhanced oil recovery from oil reservoirs where temperatures range from 70° C. to 90? C. The said microbial consortium is unique in producing a variety of metabolic products mainly CO2, methane, biosurfactant, volatile fatty acids and alcohols in the presence of specially designed nutrient medium. These metabolic products increase sweep efficiency of crude oil from oil bearing poles of rock formation. The present invention also provides a process for enhancing the oil recovery by in situ application of the said microbial consortium.
    Type: Application
    Filed: July 14, 2004
    Publication date: April 26, 2007
    Applicants: The Energy and Resources Institute, Institute of Reservoir Studies
    Inventors: Banwari Lal, Mula Ramajaneya Reddy, Anil Agnihotri, Ashok Kumar, Munish Sarbhai, Nimmi Singh, Raj Khurana, Shinben Khazanchi, Tilak Misra
  • Self-healing coating and microcapsules to make same
    Patent number: 7192993
    Abstract: A liquid self-healing coating, incorporating microcapsules filled with tailored repair formulations, repairs itself upon physical compromise after curing. In one embodiment, a commercially available paint primer is mixed with a pre-specified amount of these microcapsules. After the coating has cured on the substrate to which it is applied, any physical compromise of the cured coating results in the microcapsules bursting to release a liquid that fills and seals the compromised volume of the coating. In applications where paint is used to provide corrosion protection, the liquid contains anti-corrosion material as well as suitable diluents and film-forming compounds. In another embodiment, the microcapsules may be provided separately to enhance commercially available products.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 20, 2007
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Srinivasan Sarangapani, Ashok Kumar, Curtis Thies, Larry D. Stephenson
  • System and Method for the Identification of Chemical Mechanical Planarization Defects
    Publication number: 20070061088
    Abstract: The present invention presents a novel application of a wavelet-based multiscale method in a nanomachining process chemical mechanical planarization (CMP) of wafer fabrication. The invention involves identification of delamination defects of low-k dielectric layers by analyzing the nonstationary acoustic emission (AE) signal collected during copper damascene (Cu-low k) CMP processes. An offline strategy and a moving window-based strategy for online implementation of the wavelet monitoring approach are developed.
    Type: Application
    Filed: October 31, 2006
    Publication date: March 15, 2007
    Applicant: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Rajesh Ganesan, Tapas Das, Arun Sikder, Ashok Kumar
  • Process for the preparation of alkaline protease
    Patent number: 7186546
    Abstract: The present invention relates to a process for the preparation of alkaline protease using a fungal culture of the order entomophthorales and to the use of the said protease in the pretanning processes of leather manufacture.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: March 6, 2007
    Assignee: Council of Scientific and Industrial Research
    Inventors: Ryali Seeta Laxman, Snehal Vijay More, Meenakshi Vilas Rele, Bommaraju Seeta Rama Rao, Vithal Venkatrao Jogdand, Mala Balachandra Rao, Vasanti Vishnu Deshpande, Ramachandra Boopathy Naidu, Panchatcharam Manikandan, Dilly Ashok Kumar, James Kanagaraj, Ramalingam Samayavaram, Natesan Samivelu, Puvanakrishnan Rengarajulu