Abstract: A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a querying device. The linked list can be built, modified, or disabled by low level software, and then locked so that it appears as read-only to higher level software such as an operating system or device driver.

Abstract: A system for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data transfer back to the original requester, and the device is no longer involved.

Abstract: A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the PCI bus. This information can then be observed and used in a debugging process.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices. The central hub also communicates with a processor and system memory over additional buses. Each link bus includes a status line that allows each device connected to the same link bus to request control of the bus. The link bus protocol establishes a window in which the status signal may convey arbitration request information in a time-multiplexed manner. The protocol further includes a method of determining whether control of the bus can be transferred to a different device. Each device takes part in the decision process and thus, the arbitration method of the invention is decentralized.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving circuitry of a target device can be put into a known state during a final stage of a source strobe event such as e.g., a data transfer. Once in the known state, the source strobes are stopped on the link bus. The target device uses internal logic clocked by a system clock rather than the source strobe to continuously sample the state of the receiving circuitry to see if the state has deviated from the known state. A change detect circuit determines if the receiving circuitry has deviated from the known state and if so, detects a new source strobe event. The change detect circuit detects the new event in the less stringent clock domain, which allows greater control of the skew and asymmetry of the source strobe.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices and the central hub also communicates with a processor cluster and system memory over respective processor and memory buses. Thus, all components within the system are capable of communicating with each other through the hub. By communicating over the link buses via the link bus protocol, satellite devices can report events to other devices without dedicated wiring/pins between the devices as is currently performed in the prior art. In addition, the flushing of data buffers is governed by the protocol such that only targeted data buffers are flushed, which improves overall system performance.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices. All components within the system are capable of communicating with each other through the hub. Each link bus includes a status line that allows each device connected to the same link bus to accept, deny, or delay a data transfer on the link bus. If accepted, the same status line can be used by the transferor and target of a data transfer, if necessary, to stall or pace the transfer as needed. The link bus protocol establishes a window in which the status line may convey data transfer disconnecting or pacing status information. The protocol further includes a method of retrying or aborting transfers based on the disconnecting status information.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A system for autonomously configuring peer devices without unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, the compatibility bridge monitors the status of the configuration cycle on the host bus. The compatibility bridge determines whether and when to forward the configuration cycle to another bus, e.g., a PCI bus. The system records the presence or absence of a particular device by setting a respective bit in a scorecard register and scorecard valid register.

Abstract: A method of configuring peer devices without the unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, a BIOS initialization scans all peer devices located on the host bus. A watchdog timer times out after a predetermined duration when the intended device fails to respond to the configuration cycle. A bit corresponding to the particular device is set in a scorecard register. The compatibility bridge responds to the configuration cycle after the watchdog time-out period.

Abstract: A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.

Abstract: A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.

Abstract: A system for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data transfer back to the original requester, and the device is no longer involved.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A method for expanding the number of configuration registers available in a computer system. Unused configuration registers that correspond to non-existent functions are used for other purposes. Memory is configured to allow enumeration software to conclude that the non-existent functions do not in fact exist.

Abstract: A system for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data transfer back to the original requester, and the device is no longer involved.

Abstract: A buffer pool is described for buffering data transfers between components within a computer system. The buffer pool uses a translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The virtual address pointers are held in a translation entry table that correlates virtual and physical pointers.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap viuual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A system for autonomously configuring peer devices without unnecessary delay in boot up time using a compatibility bridge. Upon initiating a configuration cycle, the compatibility bridge monitors the status of the configuration cycle on the host bus. The compatibility bridge determines whether and when to forward the configuration cycle to another bus, e.g., a PCI bus. The system records the presence or absence of a particular device by setting a respective bit in a scorecard register and scorecard valid register.

Abstract: A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.