Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device manager.

Abstract: A method and system interfaces a plurality of bus requesters with a computer bus having a bus bandwidth. The bus bandwidth is apportioned among the plurality of bus requesters by assigning to a selected bus requester a portion of the bus bandwidth based on how much the selected bus requester used the bus during a defined period. A bus controller determines how much the selected bus requester used the bus during the fine period by monitoring the use of the bus requester during the defined period. The bus controller assigns an initial bus bandwidth portion and a target use bandwidth portion. The bus controller compares how much the selected bus requester used the bus during the defined period to the target use bandwidth portion assigned to the selected bus requester.

Abstract: Data is written to a memory subsystem in a computer system, wherein the data is supplied by an input/output (I/O) bus. The I/O bus provides a STROBE signal, the occurrence of which is indicative of a time when an I/O data word on the I/O bus is valid. A first I/O data word provided by the I/O bus, after a first occurrence of the STROBE signal, is stored in a data buffer. A memory data word is retrieved from the memory subsystem in response to the first occurrence of the STROBE signal. A second I/O data word provided by the I/O bus, after a second occurrence of the STROBE signal, is stored in the data buffer. The memory data word is modified by the first and second I/O data words to form a modified data word. Error detection information corresponding to the modified data word is generated and the modified data word and the error detection information are written to the memory subsystem.