Patents by Inventor A-Shen Chang

A-Shen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170339070
    Abstract: A cloud broker gateway interfaces with an enterprise network and one or more public cloud networks, including a first public cloud and a second public cloud. The cloud broker gateway receives a request for one or more computing resources from a tenant associated with the enterprise network, and directs the request to the first public cloud based on a brokerage policy for the tenant. The cloud broker gateway receives a response indicating the first public cloud cannot provide the one or more computing resources, and redirects the request to the second public cloud based on the brokerage policy for the tenant. The cloud broker gateway also establishes a hybrid cloud that provides access to the one or more computing resources between the second public cloud and the enterprise network.
    Type: Application
    Filed: May 23, 2016
    Publication date: November 23, 2017
    Inventors: David Wei-Shen Chang, Chiang Han Yang, Murali Anantha, Shashank Vinchurkar
  • Patent number: 9825173
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9799750
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Fai Cheng, Han-Ting Tsai, An-Shen Chang, Hui-Min Lin
  • Patent number: 9755858
    Abstract: An example method for a programmable infrastructure gateway for enabling hybrid cloud services in a network environment is provided and includes receiving an instruction from a hybrid cloud application executing in a private cloud, interpreting the instruction according to a hybrid cloud application programming interface, and executing the interpreted instruction in a public cloud using a cloud adapter. The method is generally executed in the infrastructure gateway including a programmable integration framework allowing generation of various cloud adapters using a cloud adapter software development kit, the cloud adapter being generated and programmed to be compatible with a specific public cloud platform of the public cloud.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: September 5, 2017
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Nagaraj A. Bagepalli, David Wei-Shen Chang, Abhijit Patra, Murali Anantha, Prashanth Thumbargudi
  • Patent number: 9704974
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, An-Shen Chang, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chia-Tai Lin, Chih-Tang Peng
  • Publication number: 20170193659
    Abstract: A method for evaluating skin tissue includes: obtaining a tomographic image of skin; performing a quantization process for quantizing brightness values of the tomographic image of skin to generate a quantized image; performing a binarization process on the brightness value of each image point in the quantized image according to a first threshold interval to generate a first filtered image; performing the binarization process on the brightness value of each image point in the quantized image according to a second threshold interval to generate a second filtered image; obtaining a first estimated tissue boundary according to the distribution of the bright spots in the first filtered image; obtaining a second estimated tissue boundary according to the distribution of the bright spots in the second filtered image; estimating a thickness of skin tissue according to a difference between the first and second estimated tissue boundaries.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 6, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Chang WANG, Chih-Ming CHENG, Chir-Weei CHANG, Chi-Shen CHANG, Sheng-Li CHANG
  • Publication number: 20170092215
    Abstract: A gate driving and modulating circuit, for reduced flicker on a display, includes a first discharge circuit and a plurality of interconnected gate drivers. The plurality of gate drivers is electrically coupled to ground through the first discharge circuit. Each of the plurality of gate drivers includes a second discharge circuit. The gate driving circuit performs a chamfering of a gate signal by being simultaneously discharged through the first discharge circuit and the second discharge circuit.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 30, 2017
    Inventors: LI-SHEN CHANG, CHEN-CHI YANG
  • Patent number: 9516115
    Abstract: A softphone feature interface method, system, and apparatus are provided for operating a mobile communication device as a softphone to place Internet phone calls by displaying a home user interface on a touch screen with a unified view having a display interface area and a keyboard interface area, and then displaying a second user interface on the touch screen for displaying user call information in response to receiving touch input on the home user interface of the touch screen to display a list of contacts that match a contact result search entered on the search keypad or to display a contacts user interface or voicemail user interface in response to detecting a slide operation on the home user interface or to display one or more calling methods available for selection in response to detecting a call button being pressed for a minimum specified hold time.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 6, 2016
    Assignee: Software 263 Technology (Beijing) Co., Ltd.
    Inventor: Shen Chang
  • Publication number: 20160307495
    Abstract: A scanning method of a display changes a driving order of a plurality of gate driver lines so as to reduce switching currents generated while a plurality of voltages on a plurality of source driver lines are changed. Thereby, the goal of saving power can be reached.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 20, 2016
    Inventors: Kuei-Kai CHANG, Chun-Fu LIU, Li-Shen CHANG, Lu-Yao WU
  • Publication number: 20160308027
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chia-Wei CHANG, An-Shen CHANG, Eric Chih-Fang LIU, Ryan Chia-Jen CHEN, Chia-Tai LIN, Chih-Tang PENG
  • Publication number: 20160278695
    Abstract: A virtual image display system adapted for venipuncture applications is provided. The virtual image display system includes at least one infrared light source, at least one image sensing module, and at least one virtual image display module. The at least one infrared light source is configured to emit at least one infrared light to a tissue having a vein. The at least one image sensing module is configured to receive the infrared light from the tissue so as to sense an image of the vein. The at least one virtual image display module is disposed in front of at least one eye of a user. The at least one virtual image display module includes an image display unit configured to show an image of the vein to the at least one eye of the user.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Inventors: Chy-Lin Wang, Kuo-Tung Tiao, Tian-Yuan Chen, Lung-Pin Chung, Chun-Chuan Lin, Jyh-Chern Chen, Chi-Shen Chang, Ching-Chieh Yang
  • Patent number: 9373409
    Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 21, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo-Pin Chang, Chih-Shen Chang
  • Publication number: 20160165032
    Abstract: A softphone feature interface method, system, and apparatus are provided for operating a mobile communication device as a softphone to place Internet phone calls by displaying a home user interface on a touch screen with a unified view having a display interface area and a keyboard interface area, and then displaying a second user interface on the touch screen for displaying user call information in response to receiving touch input on the home user interface of the touch screen to display a list of contacts that match a contact result search entered on the search keypad or to display a contacts user interface or voicemail user interface in response to detecting a slide operation on the home user interface or to display one or more calling methods available for selection in response to detecting a call button being pressed for a minimum specified hold time.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Applicant: SOFTWARE 263 TECHNOLOGY (BEIJING) CO., LTD.
    Inventor: Shen Chang
  • Patent number: 9323039
    Abstract: A particle manipulation system and a projection device are provided. The projection device includes an image source and a projection lens. The image source provides an image beam. The projection lens is disposed on a light path of the image beam and includes a zoom lens set and a focusing lens set. The zoom lens set is disposed on the light path of the image beam from the image source and includes at least two lens groups disposed in sequence on the light path of the image beam. The focusing lens set is disposed on the light path of the image beam. The zoom lens set is disposed between the image source and the focusing lens set. A photoconductor chip is disposed on the light path of the image beam from the projection lens.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 26, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiu-Hsiang Chen, Hsin-Hsiang Lo, Chun-Chuan Lin, Kuo-Yao Weng, Chi-Shen Chang, Jyh-Chern Chen
  • Patent number: 9324437
    Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: April 26, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo Pin Chang, Chih-Shen Chang, Hang-Ting Lue
  • Publication number: 20160035874
    Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Inventors: Chia Tai Lin, Yih-Ann Lin, An-Shen Chang
  • Publication number: 20160035424
    Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Kuo Pin Chang, Chih-Shen Chang, Hang-Ting Lue
  • Publication number: 20160012905
    Abstract: Common problems when programming 3D NAND Flash memory having alternating page orientation include the back-pattern effect and pattern-induced program disturb. Improved programming techniques may substantially reduce these problems and, in turn, increase precision when setting memory cells' threshold voltages. Provided are exemplary techniques that combine aspects of “by-word-line” programming and “by-page” programming. As such, each page may be programmed beginning with the memory cells that are closest to string select structures, and memory cells on multiple even or odd pages may be programmed substantially simultaneously.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuo-Pin Chang, Chih-Shen Chang
  • Patent number: 9223634
    Abstract: A method includes simulating network resources of a portion of a cloud in a simulated cloud within a enterprise network, the cloud being communicable with the enterprise network over a first communication channel, which may be external to the enterprise network. The method can also include simulating network behavior of the first communication channel in a second communication channel within the enterprise network, and validating application performance in the simulated cloud. Simulating network resources includes providing a cloud resources abstraction layer in the enterprise network, and allocating enterprise network resources in the enterprise network to the simulated cloud by the cloud resources abstraction layer. The method further includes adding a virtual network service appliance to the simulated cloud, and determining a change to a network topology of the enterprise network to accommodate the virtual appliance without materially impacting application performance.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 29, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: David Wei-Shen Chang, Abhijit Patra, Nagaraj A. Bagepalli
  • Patent number: 9201704
    Abstract: A method includes managing a virtual machine (VM) in a cloud extension, where the VM is part of a distributed virtual switch (DVS) of an enterprise network, abstracting an interface that is transparent to a cloud infrastructure of the cloud extension, and intercepting network traffic from the VM, where the VM can communicate securely with the enterprise network. The cloud extension comprises a nested VM container (NVC) that includes an emulator configured to enable abstracting the interface, and dual transmission control protocol/Internet Protocol stacks for supporting a first routing domain for communication with the cloud extension, and a second routing domain for communication with the enterprise network. The NVC may be agnostic with respect to operating systems running on the VM. The method further includes migrating the VM from the enterprise network to the cloud extension through suitable methods.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 1, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: David Wei-Shen Chang, Abhijit Patra, Nagaraj A. Bagepalli, Murali Anantha, Jason Zhen Zhang