Patents by Inventor A. VIJAY

A. VIJAY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180053263
    Abstract: The present disclosure discloses a method and a system for determining quantity of food consumed by users. The method comprising receiving one or more inputs from a first set of sensors and a second set of sensors associated with the determination unit, where the first set of sensors and the second set of sensors monitor one or more users and food served to the one or more users respectively, identifying each type of food from the food served, identifying each of the one or more users and actions performed by each of the one or more users to consume the food and determining quantity of each type of food consumed by each of the one or more users based on the identified actions performed by each of the one or more users.
    Type: Application
    Filed: September 29, 2016
    Publication date: February 22, 2018
    Inventors: Vijay KUMAR, Ramya KOLLI, Shagun RAI
  • Publication number: 20180050446
    Abstract: The present disclosure discloses a stapling device, comprising an activation unit configured to sense at least one of a movement of the stapling device, a position of a switch or a signal from a timer. There is a detection unit that is activated based on a signal from the activation unit to generate an input data. The stapling device further comprises a processing unit to determine number of pins in the stapling device, by comparing the input data with a pre-configured data and a display unit interfaced with the processing unit, to indicate status of the pins in the stapling device, wherein the status is based on the determined number of pins in the stapling device. Thus the stapling device of the present disclosure identifies the exhaustion of pins and accordingly enables timely replenishment of the stapling device with pins.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 22, 2018
    Inventors: Vijay KUMAR, Thomas Chittakattu NINAN, Shagun RAI
  • Publication number: 20180051636
    Abstract: A power system for powering a load is provided. The power system includes a plurality of power sources with each power source including an engine. A SCR system is associated with the engine of at least one of the plurality of power sources. A controller is in communication with the plurality of power sources. The controller is configured to receive engine operation information, emission output information associated with each engine and conversion efficiency information associated with the SCR system and selectively apportion the power demand presented by the load between each of the plurality of power sources based on minimizing total engine emissions across the plurality of power sources and using the engine operation information, the emission output information and the conversion efficiency information.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Applicant: Caterpillar Inc.
    Inventors: Yanchai Zhang, Michael A. Snopko, Perry D. Converse, Vijay Janardhan, Insu Chang
  • Publication number: 20180051315
    Abstract: The present invention provides, among other things, methods and compositions for determining enzyme kinetic parameters (e.g., Vmax, Km, and specific activity, etc.) indicative of clinically relevant properties of glucocerebrosidase using a physiologically relevant substrate, in particular, a substrate that is representative of substrates that typically accumulate in patients suffering from Gaucher disease such as glucosylceramide. Thus, the present invention is particularly useful to measure a kinetic parameter relating to the activity of glucocerebrosidase in a drug substance, drug product, and stability sample for enzyme replacement therapy.
    Type: Application
    Filed: December 16, 2015
    Publication date: February 22, 2018
    Applicant: Shire Human Genetic Therapies, Inc.
    Inventors: Peter Bernhardt, Chen-Chung Willy Yen, Vijay Chhajlani
  • Publication number: 20180051083
    Abstract: Described herein are novel compositions comprising bispecific and multispecific polypeptide agents, and methods using these agents for targeting cells, such as functionally exhausted or unresponsive immune cells, that co-express the inhibitory receptors PD-1 and TIM-3. These compositions and methods are useful for the treatment of chronic immune conditions, such as persistent infections or cancer.
    Type: Application
    Filed: November 3, 2017
    Publication date: February 22, 2018
    Applicant: The Brigham and Women's Hospital, Inc.
    Inventors: Vijay K. KUCHROO, Ana C. ANDERSON
  • Publication number: 20180051376
    Abstract: A method of making an article using an additive manufacturing technique includes depositing a powder. The powder includes particles formed from an article material and having particle surfaces. A coating formed from a sacrificial coating is deposited over the particle surface. The sacrificial material has a composition that is different from the composition of the article material and is separated from the article material during fusing of the article material into a layer of an additively manufactured article.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Inventors: John A. Sharon, Ying She, Paul Sheedy, James T. Beals, Vijay Narayan Jagdale
  • Publication number: 20180054873
    Abstract: A calibration method comprising, for each of one or more light sensors: (a) under influence of one or more substantially non-zero illumination levels in the target environment, using the light sensor to measure the sensed light level corresponding to each of these one or more illumination levels; (b) receiving a template light level value corresponding to each of the one or more illumination levels, representing the light level at a target location in the target environment substantially removed in space from the location of the light sensor, each of the one or more template light level values being assumed for the environment rather than measured by a light meter; and (c) determining a relationship between the sensed light level and the light level experienced at the target location, based on an evaluation of the one or more sensed levels relative to the one or more template light level values.
    Type: Application
    Filed: March 2, 2016
    Publication date: February 22, 2018
    Inventors: ASHISH VIJAY PANDHARIPANDE, DAVID RICARDO CAICEDO FERNANDEZ
  • Publication number: 20180050293
    Abstract: A substrate for use in a filter media including, for example, in a hydrocarbon fluid-water separation filter; methods of identifying the substrate; methods of making the substrate; methods of using the substrate; and methods of improving the roll off angle of the substrate. In some embodiments, the substrate includes a hydrophilic group-containing polymer or a hydrophilic group-containing polymer coating.
    Type: Application
    Filed: August 16, 2017
    Publication date: February 22, 2018
    Inventors: Bradly G. Hauser, Stephen K. Sontag, Davis B. Moravec, Stuti S. Rajgarhia, Andrew J. Dallas, Vijay K. Kapoor, Aflal Rahmathullah, Charles S. Christ, Joseph M. Block
  • Publication number: 20180053628
    Abstract: Separation grids for plasma processing apparatus are provided. In some embodiments, a plasma processing apparatus includes a plasma chamber. The plasma processing apparatus includes a processing chamber. The processing chamber can be separated from the plasma chamber. The apparatus can include a separation grid. The separation grid can separate the plasma chamber and the processing chamber. The apparatus can include a temperature control system. The temperature control system can be configured to regulate the temperature of the separation grid to affect a uniformity of a plasma process on a substrate. In some embodiments, a separation grid can have a varying thickness profile across a cross-section of the separation grid to affect a flow of neutral species through the separation grid.
    Type: Application
    Filed: May 10, 2017
    Publication date: February 22, 2018
    Inventors: Vijay M. Vaniapura, Shawming Ma, Vladimir Nagorny, Ryan M. Pakulski
  • Publication number: 20180054342
    Abstract: A method and apparatus provide reception of control signaling in a wireless communication network. A preamble transmission can be detected from a second device in a first set of at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol starting with a first OFDM symbol in a subframe received on a secondary serving cell operating on an unlicensed carrier, the first OFDM symbol having a first Cyclic Prefix (CP). A second OFDM symbol in the subframe can be determined such that the second OFDM symbol immediately follows the first set of OFDM symbols. Downlink Control Information (DCI) containing a Physical Downlink Shared Channel (PDSCH) resource assignment can be decoded in a second set of OFDM symbols beginning with the second OFDM symbol, the second set of OFDM symbols having a second CP. The duration of the first CP is larger than the duration of the second CP.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: Ravikiran Nory, Vijay Nangia, Ajit Nimbalker
  • Patent number: 9899264
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Patent number: 9899089
    Abstract: A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: February 20, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ryan Tasuo Hirose, Fredrick B. Jenne, Vijay Raghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan I. Georgescu, Leonard Vasile Gitlan, James Paul Myers
  • Patent number: 9898477
    Abstract: A method, article of manufacture, and apparatus for providing a site cache manager is discussed. Data objects may be read from a site cache rather than an authoritative object store. This provides performance benefits when a client reading the data has a better connection to the site cache than to the authoritative object store. The site cache manager controls the volume of stored data on the site cache to enhance performance by increasing the frequency of data object being read from or written to the site cache rather than the authoritative object store.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 20, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Vijay Panghal
  • Patent number: 9895682
    Abstract: A catalyst composition comprises a self-bound zeolite and a Group 12 transition metal selected from the group consisting of Zn, Cd, or a combination thereof, the zeolite having a silicon to aluminum ratio of at least about 10, the catalyst composition having a micropore surface area of at least about 340 m2/g, a molar ratio of Group 12 transition metal to aluminum of about 0.1 to about 1.3, and at least one of: (a) a mesoporosity of greater than about 20 m2/g; (b) a diffusivity for 2,2-dimethylbutane of greater than about 1×10?2 sec?1 when measured at a temperature of about 120° C. and a 2,2-dimethylbutane pressure of about 60 torr (about 8 kPa).
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: February 20, 2018
    Assignee: EXXONMOBIL RESEARCH AND ENGINEERING COMPANY
    Inventors: Stephen J. McCarthy, Rohit Vijay, Brett Loveless
  • Patent number: 9899048
    Abstract: A flexible printed circuit for a storage drive assembly is provided. The flexible printed circuit includes a stiffener layer having a first stiffener region, and a second stiffener region separated from the first stiffener region by a hinge region, a first insulation layer disposed on the stiffener layer, a conductive electrode layer disposed on the first insulation layer; and a second insulation layer disposed on the conductive electrode layer, wherein the hinge region is formed from the first insulation layer, the conductive electrode layer and the second insulation layer.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 20, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Mukund Vijay
  • Patent number: 9898196
    Abstract: A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: February 20, 2018
    Assignee: Virident Systems, LLC
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Swamy Gowda
  • Patent number: 9898268
    Abstract: A method and system for enhanced local commoning optimization of compilation of a program. Commoning of volatiles within an extended block for a particular memory model associated with a particular programming language is performed, using a two pass approach. Within a first pass, a determination is made as to where in the program to evaluate volatile expressions that can be commoned. In a second pass, all remaining expressions that are not volatile expressions are commoned.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Craik, Patrick R. Doyle, Vijay Sundaresan
  • Patent number: 9896982
    Abstract: A power system for powering a load is provided. The power system includes a plurality of power sources with each power source including an engine. A SCR system is associated with the engine of at least one of the plurality of power sources. A controller is in communication with the plurality of power sources. The controller is configured to receive engine operation information, emission output information associated with each engine and conversion efficiency information associated with the SCR system and selectively apportion the power demand presented by the load between each of the plurality of power sources based on minimizing total engine emissions across the plurality of power sources and using the engine operation information, the emission output information and the conversion efficiency information.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: February 20, 2018
    Assignee: Caterpillar Inc.
    Inventors: Yanchai Zhang, Michael A. Snopko, Perry D. Converse, Vijay Janardhan, Insu Chang
  • Publication number: 20180049204
    Abstract: A method and apparatus include receiving a resource allocation in a control information message. The resource allocation includes one or more resource blocks, wherein each of the one or more resource blocks comprises a plurality of subcarriers. An indication is received in the control information message identifying whether one or more guard subcarriers are present on a respective one or more of the edges of at least one resource block of the resource allocation.
    Type: Application
    Filed: August 11, 2017
    Publication date: February 15, 2018
    Inventors: Ravikiran Nory, Vijay Nangia, Robert T Love, Ravi Kuchibhotla
  • Publication number: 20180047640
    Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 15, 2018
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan