Patents by Inventor A. VIJAY

A. VIJAY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9889915
    Abstract: A control system to optimize response time of a plurality of engines of a machine is provided. The control system includes a controller configured to determine a first engine group and a second engine group based on data regarding response time characteristics of the plurality of engines, control the first engine group to increase output power of the machine when the output power of the machine is below a predetermined power output threshold, and control the second engine group to increase output power of the machine responsive to the output power of the machine reaching the predetermined power output threshold. A response time of the first engine group is faster than a response time of the second engine group when the output power of the machine is below the predetermined power output threshold.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 13, 2018
    Assignee: Caterpillar Inc.
    Inventors: Yanchai Zhang, Michael A. Snopko, Insu Chang, Vijay Janardhan, Perry D. Converse
  • Patent number: 9892802
    Abstract: A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: February 13, 2018
    Assignee: Apple Inc.
    Inventors: Bo Yang, Andrew J. Copperhall, Bibo Li, Vijay M. Bettada
  • Patent number: 9893636
    Abstract: Systems and methods for operating improved flyback converters are disclosed, in which leakage energy is returned to the input power source rather than to the output load, while still achieving zero voltage switching (i.e., ZVS) operation. In some embodiments, the improved converters may transfer the energy stored in the leakage inductance to a snubber capacitor(s) at the instant of turning off of the control switch. Further, the improved converter embodiments may also retain the stored energy in the snubber capacitor(s) when the power is being delivered to the load by the secondary circuits. The improved converter embodiments may start the transfer of leakage energy stored in the snubber capacitor(s) to the primary winding once the energy stored in the transformer is delivered to the load. Finally, the improved converter embodiments may intelligently control their active clamp switches such that all leakage inductance energy is returned to the input source.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 13, 2018
    Assignee: Apple Inc.
    Inventor: Vijay Phadke
  • Patent number: 9892105
    Abstract: A method of annotating an electronic message executes at a computing device having one or more processors and memory. The memory stores one or more programs configured for execution by the one or more processors. The device displays a user interface for an electronic messaging application. The user interface includes a list of messages received by the user, and each displayed message includes a respective message summary that is displayed. The device receives from the user a description of a first task associated with a first message of the displayed messages. The user provides the description using a control in the user interface. The device stores the description as a first annotation associated with the first message and updates the displayed messages in the list of messages. For the first message, the device displays the first annotation as a substitute for the message summary.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 13, 2018
    Assignee: Google LLC
    Inventors: Vijay Umapathy, Xander Pollock, Ryan Proch, Taylor Kourim, Liam Asher Segel-Brown
  • Patent number: 9891679
    Abstract: A single phase redundant power supply system may include a first power supply having an input coupled to a first phase voltage in a polyphase power distribution system and an output coupled to a load for supplying an amount of DC power to the load, and a second power supply having an input for coupling to a second phase voltage in the polyphase power distribution system and an output coupled to the load for supplying an amount of DC power to the load. At least the first power supply is configured to reduce phase current imbalances in the polyphase power distribution system by adjusting the amount of DC power supplied to the load by the first power supply and the amount of DC power supplied to the load by the second power supply.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 13, 2018
    Assignee: ASTEC INTERNATIONAL LIMITED
    Inventors: Vijay Gangadhar Phadke, Robert Lee Myers
  • Patent number: 9893737
    Abstract: An apparatus includes a series of analog-to-digital converter (ADC) stages and a comparison circuit coupled to a first ADC stage. The first ADC stage may be configured to compare an input signal to one or more conversion thresholds to generate a result. The first ADC stage may also be configured to generate an output signal based on a value of the result. In response to an assertion of a reset signal, the first ADC stage may be configured to set a level of the output signal voltage to a particular voltage. The comparison circuit may be configured to assert the reset signal in response to a determination that the input signal voltage exceeds an operating range defined by an upper overload threshold voltage and a lower overload threshold voltage.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 13, 2018
    Assignee: Apple Inc.
    Inventors: Mansour Keramat, KiYoung Nam, Vijay Srinivas
  • Publication number: 20180040709
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Publication number: 20180040081
    Abstract: One embodiment provides a method including: utilizing at least one processor to execute computer code that performs the steps of: obtaining a user's status update posted on a social networking site; analyzing the status update to obtain at least one element of travel information of a travel plan included within the status update, wherein the travel information comprises the elements of: a starting location, an ending location, and a mode of transportation; predicting elements missing from the travel information, the missing elements comprising travel information not included in the status update, wherein the predicting comprises analyzing a secondary information source for the missing elements and wherein the predicting comprises assigning a confidence score to the prediction; and providing a dynamic travel update identifying travel progress of the user, compared to the travel plan based upon the obtained at least one element and the predicted missing elements, wherein the dynamic travel update comprises the
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Subhajit Bhuiya, Vijay Ekambaram, Ashish Kumar Mathur, Sarbajit K. Rakshit
  • Publication number: 20180040710
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Publication number: 20180039765
    Abstract: One embodiment provides a method, including: utilizing at least one processor to execute computer code that performs the steps of: receiving motion sensor information from a plurality of sensors on a wearable device; identifying, based on the motion sensor information, a motion pattern corresponding to an activity of a user; comparing the motion pattern to a plurality of stored motion patterns; determining, based on the comparing, if the motion pattern matches one of the stored motion patterns that is identified as a motion pattern of a sensitive activity; and modifying, whether the motion pattern matches one of the stored motion pattern identified as a motion pattern of a sensitive activity. Other aspects are described and claimed.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Vijay Ekambaram, Vikas Joshi, Pratyush Kumar
  • Publication number: 20180040909
    Abstract: A solid oxide fuel cell (SOFC) includes a cathode electrode, a solid oxide electrolyte and an anode electrode containing a first portion having a cermet containing a nonzero volume percent of a nickel containing phase and a nonzero volume percent of a ceramic phase and a second portion having a cermet containing a nonzero volume percent of a nickel containing phase and a nonzero volume percent of a ceramic phase, such that the first portion is located between the electrolyte and the second portion. The SOFC is an electrolyte-supported SOFC and the first portion of the anode electrode contains a lower ratio of the nickel containing phase to the ceramic phase than the second portion of the anode electrode. The first portion of the anode electrode has a porosity of 5-30 volume percent and the second portion of the anode electrode has a porosity of 31-60 volume percent.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Michael GASDA, Chockkalingam KARUPPAIAH, Tad ARMSTRONG, Vijay RADHAKRISHNAN, Emad EL BATAWI
  • Publication number: 20180040708
    Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Vijay Narayanan, Yohei Ogawa, John Rozen
  • Publication number: 20180039716
    Abstract: A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system is disclosed. The method includes categorizing a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category; identifying a set of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, each target design memory block in the set is identified from either the overlapping category or the non-overlapping category; designing semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; implementing the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device.
    Type: Application
    Filed: September 26, 2016
    Publication date: February 8, 2018
    Inventor: Kodavalla Vijay Kumar
  • Publication number: 20180042036
    Abstract: Described embodiments include a system that includes a network interface and a processor. The network interface is configured to receive, at a first time, a packet transmitted from a source communication terminal over a communication network en route to a target communication terminal, before the packet passes through a particular portion of the communication network, and to receive the packet at a second time, after the packet has passed through the particular portion of the communication network. The processor is configured to delay the packet, subsequently to the packet being received at the second time, by a delay duration that is a decreasing function of a duration between the first time and the second time, and to send the delayed packet, subsequently, via the network interface, en route to the target communication terminal. Other embodiments are also described.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Oren Sadeh, Nery Strasman, Vijay Devarapalli
  • Publication number: 20180039621
    Abstract: A system includes a computing device that includes a memory configured to store instructions. The system also includes a processor to execute the instructions to perform operations that include receiving data representing textual information input into a user device. Operations also include analyzing the data to determine the contextual meaning of the textual information, and producing one or more messages to present information at one or more other user devices using the contextual meaning of the textual information.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 8, 2018
    Inventors: Evan Scronce, Neeraj Gulati, Anand Vijay, Sohaj Singh Brar, Ashutosh Singh Rawat, Prasun Raj Moolambally
  • Patent number: 9887891
    Abstract: A method for generating a graph segment providing a gist or summary of an online social network conversation may include generating a graph of the online social network conversation. The graph of the online social network conversation may include a plurality of nodes and each node may be connected to at least one other node by an edge. Each node may represent a message of the online social network conversation and each edge may correspond to an action by a participant in the online social network conversation. The method may also include determining an edge weight for each edge and analyzing the graph of the online social network conversation using at least the edge weight of at least some edges. The method may additionally include generating a graph segment that provides a gist or summary of the online social network conversation based on the analysis.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alaa Abou Mahmoud, Paul R. Bastide, Vijay Francis, Fang Lu
  • Patent number: 9887121
    Abstract: A protective cover for an electrostatic chuck may include a conductive wafer and a plasma resistant ceramic layer on at least one surface of the conductive wafer. The plasma resistant ceramic layer covers a top surface of the conductive wafer, side walls of the conductive wafer and an outer perimeter of a bottom surface of the conductive wafer. Alternatively, a protective cover for an electrostatic chuck may include a plasma resistant bulk sintered ceramic wafer and a conductive layer on a portion of a bottom surface of the plasma resistant bulk sintered ceramic wafer, wherein a perimeter of the bottom surface is not covered.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: February 6, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Vijay D. Parkhe
  • Patent number: 9886793
    Abstract: A method and system for improving three dimensional video visualization is provided. The method includes receiving a video file and extracting metadata and contextual analysis data of the video file. Dimensions describing attributes associated with the video file are identified and use case data comprising text data and associated metadata describing activities occurring is the video file is retrieved. The dimensions are associated with the use case data and a group of relevant dimensions are extracted from the use case data. The dimensions are correlated with the group of relevant dimensions and a group of common dimensions is extracted from the dimensions and group of relevant dimensions. Three dimensions are selected from the group of common dimensions and a three dimensional block structure illustrating the three dimensions and the remaining dimensions is generated and presented to a user via a graphical user interface.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Vijay Ekambaram, Sarbajit K. Rakshit
  • Patent number: 9885041
    Abstract: The invention relates to methods and uses of modulating fetal hemoglobin expression (HbF) in a hematopoietic progenitor cells via inhibitors of BCL11A expression or activity, such as RNAi and antibodies.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 6, 2018
    Assignees: The Children's Medical Center Corporation, President and Fellows of Harvard College
    Inventors: Stuart H. Orkin, Vijay G. Sankaran
  • Patent number: 9888214
    Abstract: Systems and methods for streaming video and/or audio from multiple devices are provided. A camera may include an optical sensor, a wireless communication device, and a processor configured to establish a first connection with a remote location, establish a second connection with one or more other cameras, and stream video from the cameras to the remote location. The remote location may be, for example, a remote website, a remote server, or a remote client device. The camera may be further configured to provide control signals to the other cameras, such as for controlling applications running on the other cameras.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 6, 2018
    Assignee: Logitech Europe S.A.
    Inventors: John Bateman, Oleg Ostap, Oliver Hoheisel, David Kim, Vijay Karnataki