Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract: A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×108 cm?2 to be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

Abstract: A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

Abstract: A copper interconnect oh a semiconductor substrate comprises a dielectric layer having a trench, a noble metal layer on the dielectric layer within the trench, and a copper interconnect on the noble metal layer. The noble metal layer has a thickness that is between 3 ? and 100 ? and a density that is greater than or equal to 5 g/cm3. The copper interconnect may be formed by etching a trench into the dielectric layer, pulsing a noble metal containing precursor proximate to the semiconductor substrate, and pulsing a reactive gas proximate to the semiconductor substrate, wherein the reactive gas reacts with the precursor to form a noble metal layer on the dielectric layer. A copper layer may then be deposited atop the noble metal layer and planarized. The noble metal layer functions as a barrier to copper diffusion and provides a surface upon which the copper metal can nucleate.

Abstract: Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk metal and the dielectric layer. The barrier layer may include one or more metals selected from iridium, platinum, palladium, rhodium, osmium, gold, silver, rhenium, ruthenium, tungsten, and nickel.

Abstract: A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.