Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.

Abstract: In at least one embodiment, a controller of a non-volatile memory having a plurality of blocks of physical memory estimates a current value of a block health metric of the particular block based on a previous value of the block health metric and a reference block wear curve. The controller assigns the particular block a health grade based on the estimated current value of the block health metric and performs data placement in the block in accordance with the assigned health grade. The controller may calibrate a set of read threshold voltages of the particular block prior to estimating the current value of the block health metric.

Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

Abstract: A controller performs background reads of multiple physical pages of a selected physical block of a non-volatile memory. The controller detects asymmetric transient errors in a physical page among the multiple physical pages based on a bit error rate (BER) observed in the background read of the physical page. In response to detecting the asymmetric transient errors, the controller mitigates the detected asymmetric transient errors by relocating valid logical pages of data from the physical page to another physical block of the non-volatile memory and by retaining valid logical pages of data programmed into other physical pages of the selected physical block.

Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.

Abstract: A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: A computer-implemented method, according to one embodiment, includes: retrieving a physical block address corresponding to a logic block address, extracting information from the physical block address, and performing a lookup operation in cache using the extracted information. A range check of the physical block address is further performed in response to the lookup operation succeeding, while data is read from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, as well as parallel writes to different non-volatile memory channels. The cache architecture further supports pipelining of the parallel writes to different non-volatile memory planes. Moreover, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.

Abstract: A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to: retrieve a physical block address corresponding to a logic block address; extract information from the physical block address; perform a lookup operation in cache using the extracted information; perform a range check of the physical block address in response to the lookup operation succeeding; and read data from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, in addition to supporting parallel writes to different non-volatile memory channels. The cache architecture also supports pipelining of the parallel writes to different non-volatile memory planes. The non-volatile memory controller is also configured to perform a direct memory lookup in the cache based on a physical block address.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: In at least one embodiment, a controller of a non-volatile memory array iteratively performs a merged background management process independently of any host system's demand requests targeting the memory array. During an iteration of the merged background management process, the controller performs a read sweep by reading data from each of a plurality of page groups within the memory array and recording page group error statistics regarding errors detected by the reading for each page group, where each page group is formed of a respective set of one or more physical pages of storage in the memory array. During the iteration of the merged background management process, the controller employs the page group error statistics recorded during the read sweep in another background management function.

Abstract: An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.

Abstract: An apparatus, according to one embodiment, includes non-volatile memory configured to store data, and a controller and logic integrated with and/or executable by the controller, the logic being configured to: determine, by the controller, that at least one block of the non-volatile memory and/or portion of a block of the non-volatile memory meets a retirement condition, re-evaluate, by the controller, the at least one block and/or the portion of a block to determine whether to retire the at least one block and/or the portion of a block, indicate, by the controller, that the at least one block and/or the portion of a block remains usable when a result of the re-evaluation is not to retire the block, and indicate, by the controller, that the at least one block and/or the portion of a block is retired when the result of the re-evaluation is to retire the block.

Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.

Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.

Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.

Abstract: A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining a first open logical erase block for user writes, and a second open logical erase block for relocate writes. A first data stream having the user writes is received, and transferred to the first open logical erase block. A second data stream having the relocate writes is also received, and transferred to the second open logical erase block. Furthermore, a third data stream is received, and is mixed with the first, second, and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream.

Abstract: According to one embodiment, a method includes issuing a read request to read one or more units of data from at least one non-volatile random access memory (NVRAM) device. The read request includes one or more read voltage thresholds. The method also includes receiving the one or more data units and read command parameters used to read the one or more data units from the at least one NVRAM device. Moreover, the method includes storing error-free data units, the read command parameters used to read the error-free data units from the at least one NVRAM device, and a read completion status to one of a plurality of read buffers. The read completion status indicates a completed read when a data unit is error-free and indicates an incomplete read when a data unit is errored.

Abstract: A computer-implemented method, according to one embodiment, includes: maintaining, by a processor, a first open logical erase block for user writes; maintaining, by the processor, a second open logical erase block for relocate writes; receiving, by the processor, a first data stream having the user writes; transferring, by the processor, the first data stream to the first open logical erase block; receiving, by the processor, a second data stream having the relocate writes; and transferring, by the processor, the second data stream to the second open logical erase block. Moreover, the first and second open logical erase blocks are different logical erase blocks. Other systems, methods, and computer program products are described in additional embodiments.