Patents by Inventor Aaron R. Wilson
Aaron R. Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11925902Abstract: A thermally reflective membrane apparatus comprises a housing structure, and a thermally reflective membrane contained within the housing structure. The thermally reflective membrane comprises a semipermeable structure, and a porous, thermally reflective structure physically contacting the semipermeable structure. The porous, thermally reflective structure comprises discrete thermally reflective particles, and a binder material coupling the discrete thermally reflective particles to one another and the semipermeable structure. A fluid treatment system and method of treating a fluid are also described.Type: GrantFiled: September 1, 2020Date of Patent: March 12, 2024Assignee: Battelle Energy Alliance, LLCInventors: John R. Klaehn, Christopher J. Orme, Aaron D. Wilson, Birendra Adhikari, Frederick F. Stewart, Seth W. Snyder
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Patent number: 11744076Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: May 25, 2022Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventors: Vinayak Shamanna, Lifang Xu, Aaron R. Wilson
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Publication number: 20230118763Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: December 16, 2022Publication date: April 20, 2023Applicant: Micron Technology, Inc.Inventors: David H. Wells, Aaron R. Wilson, Paolo Tessariol
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Patent number: 11563024Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: August 25, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: David H. Wells, Aaron R. Wilson, Paolo Tessariol
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Publication number: 20220293631Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: May 25, 2022Publication date: September 15, 2022Applicant: Micron Technology, Inc.Inventors: Vinayak Shamanna, Lifang Xu, Aaron R. Wilson
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Patent number: 11380705Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: February 7, 2020Date of Patent: July 5, 2022Assignee: Micron Technology, Inc.Inventors: Vinayak Shamanna, Lifang Xu, Aaron R. Wilson
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Publication number: 20220068952Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Applicant: Micron Technology, Inc.Inventors: David H. Wells, Aaron R. Wilson, Paolo Tessariol
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Publication number: 20210249433Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: February 7, 2020Publication date: August 12, 2021Applicant: Micron Technology, Inc.Inventors: Vinayak Shamanna, Lifang Xu, Aaron R. Wilson
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Patent number: 10615174Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: GrantFiled: June 7, 2019Date of Patent: April 7, 2020Assignee: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Publication number: 20190312056Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: ApplicationFiled: June 7, 2019Publication date: October 10, 2019Applicant: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Patent number: 10381377Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: GrantFiled: July 20, 2018Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Publication number: 20180331120Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: ApplicationFiled: July 20, 2018Publication date: November 15, 2018Applicant: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Patent number: 10121799Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: GrantFiled: December 21, 2017Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Publication number: 20180114795Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: ApplicationFiled: December 21, 2017Publication date: April 26, 2018Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Patent number: 9893083Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.Type: GrantFiled: October 13, 2016Date of Patent: February 13, 2018Assignee: Micron Technology, Inc.Inventors: Fei Wang, Tom J. John, Kunal Shrotri, Anish A. Khandekar, Aaron R. Wilson, John D. Hopkins, Derek F. Lundberg
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Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Patent number: 9305938Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.Type: GrantFiled: August 12, 2015Date of Patent: April 5, 2016Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson -
Patent number: 9219001Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: July 26, 2013Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells
Publication number: 20150348991Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson -
Patent number: 9136278Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.Type: GrantFiled: November 18, 2013Date of Patent: September 15, 2015Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson
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Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells
Publication number: 20150140753Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson