Patents by Inventor Aaron R. Wilson
Aaron R. Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Patent number: 8946076Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson -
Publication number: 20140264152Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.Type: ApplicationFiled: May 29, 2014Publication date: September 18, 2014Applicant: Micron Technology, Inc.Inventors: Aaron R. Wilson, Mark Kiehlbauch
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Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells
Publication number: 20140273462Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson -
Publication number: 20130309839Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: July 26, 2013Publication date: November 21, 2013Applicant: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 8497530Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: March 19, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 8419958Abstract: Apparatus, systems and methods for plasma etching substrates are provided that achieve dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be integrated into known plasma processing systems.Type: GrantFiled: May 11, 2010Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventor: Aaron R. Wilson
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Publication number: 20120175748Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Publication number: 20120104550Abstract: A contact formed in accordance with a process for etching a insulating material to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating material to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating material is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, where the first gaseous etchant has a lower molecular weight than the second gaseous etchant.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: Aaron R. Wilson
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Patent number: 8138526Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: November 11, 2010Date of Patent: March 20, 2012Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 8093725Abstract: A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating layer is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1, where the first gaseous etchant has a lower molecular weight than the second gaseous etchant.Type: GrantFiled: September 29, 2009Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventor: Aaron R. Wilson
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Patent number: 7948030Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: September 3, 2010Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Publication number: 20110057269Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 7879659Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: July 17, 2007Date of Patent: February 1, 2011Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Publication number: 20100327369Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7857982Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.Type: GrantFiled: July 19, 2005Date of Patent: December 28, 2010Assignee: Micron Technology, Inc.Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
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Patent number: 7808041Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: December 1, 2009Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Publication number: 20100213172Abstract: Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be readily integrated into known plasma processing systems.Type: ApplicationFiled: May 11, 2010Publication date: August 26, 2010Inventor: Aaron R. Wilson
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Patent number: 7713430Abstract: Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be readily integrated into known plasma processing systems.Type: GrantFiled: February 23, 2006Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventor: Aaron R. Wilson
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Publication number: 20100072557Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: December 1, 2009Publication date: March 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7670958Abstract: An etching method includes applying a photoresist over a substrate, forming an opening in the photoresist, and etching the substrate under the opening using a plasma generated with a gas composition containing argon and an amount of higher atomic mass inert gas. The amount may be effective to increase photoresist stability compared to otherwise identical etching lacking any of the higher atomic mass inert gas. The photoresist may have a composition sensitized to an actinic energy wavelength of 248 nm or less. A method of increasing the stability of 248 nm or less photoresist during RIE includes providing a means for reducing electron temperature of a plasma and etching a substrate exposed through photoresist openings without substantially destabilizing the photoresist.Type: GrantFiled: August 1, 2006Date of Patent: March 2, 2010Assignee: Micron Technology, Inc.Inventor: Aaron R. Wilson