Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

Abstract: Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.

Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.

Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. The microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Microelectronic devices include a stack having a vertically alternating sequence of insulative and conductive structures arranged in tiers. Slit structures extend through the stack, dividing the stack into blocks. A first series of stadiums—within the stack of a first block of a pair of the blocks—includes at least one stadium having multiple parallel sets of staircases. A second series of stadiums—within the stack of a second block of the pair of blocks—includes at least one additional stadium having additional multiple parallel sets of staircases that are mirrored, across one of the slit structures, to the multiple parallel sets of staircases of the first series. In methods of fabrication, common mask openings are used to form the mirrored staircase profiles once stadiums are already at substantially their final depths in the stack structure. Electronic systems are also disclosed.

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

Abstract: Control logic in a memory device receives a request to program data to a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and identifies a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data. The control logic further causes a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block, and causes a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.