Patents by Inventor Aaron S. Yip
Aaron S. Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230059543Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.Type: ApplicationFiled: August 15, 2022Publication date: February 23, 2023Inventors: Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard
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Patent number: 11587919Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: July 17, 2020Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Kunal R. Parekh, Akira Goda
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Publication number: 20230039026Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.Type: ApplicationFiled: August 9, 2021Publication date: February 9, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Hao T. Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda, Aaron S. Yip, Yoshihiko Kamata
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Patent number: 11574685Abstract: Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.Type: GrantFiled: July 28, 2021Date of Patent: February 7, 2023Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 11562791Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.Type: GrantFiled: August 9, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Hao T. Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda, Aaron S. Yip, Yoshihiko Kamata
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Patent number: 11545456Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.Type: GrantFiled: August 13, 2020Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Akira Goda, Kunal R. Parekh, Aaron S. Yip
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Patent number: 11404125Abstract: Methods of operating a memory, and memories configured to perform such methods, might include applying a programming pulse having a plurality of different voltage levels to a selected access line during a programming operation, and for each group of memory cells of a plurality of groups of memory cells of a plurality of memory cells selected for programming, enabling that group of memory cells for programming during a respective portion of the duration of the programming pulse of a corresponding voltage level of the plurality of different voltage levels, wherein memory cells of the plurality of memory cells selected for programming and having a particular intended data state are members of more than one of the groups of memory cells, and at least one of the groups of memory cells comprises a memory cell having the particular intended data state and a memory cell having a different intended data state.Type: GrantFiled: May 17, 2021Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Publication number: 20220238554Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Inventor: Aaron S. Yip
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Patent number: 11335700Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.Type: GrantFiled: March 22, 2021Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 11329058Abstract: A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the seleType: GrantFiled: November 2, 2020Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Publication number: 20220076751Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Aaron S. Yip, Tomoko Ogura Iwasaki
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Publication number: 20220052010Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: August 13, 2020Publication date: February 17, 2022Inventors: Akira Goda, Kunal R. Parekh, Aaron S. Yip
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Publication number: 20220020736Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Inventors: Aaron S. Yip, Kunal R. Parekh, Akira Goda
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Publication number: 20210366527Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: Aaron S. Yip, Theodore T. Pekny
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Publication number: 20210358554Abstract: Apparatus might include a controller configured to cause the apparatus to program a plurality of memory cells from a first data state to a second data state higher than the first data state, determine a respective first voltage level of a control gate voltage deemed to cause each memory cell of a first and second subset of memory cells of the plurality of memory cells to reach the second data state, determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the first subset of memory cells to reach a third data state higher than the second data state, and determine a respective second voltage level of a control gate voltage deemed sufficient to cause each memory cell of the second subset of memory cells to reach a fourth data state higher than the third data state.Type: ApplicationFiled: July 28, 2021Publication date: November 18, 2021Applicant: MICRON TECHNOLOGY, INC.Inventor: Aaron S. Yip
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Publication number: 20210288071Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.Type: ApplicationFiled: March 22, 2021Publication date: September 16, 2021Inventor: Aaron S. Yip
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Publication number: 20210272633Abstract: Methods of operating a memory, and memories configured to perform such methods, might include applying a programming pulse having a plurality of different voltage levels to a selected access line during a programming operation, and for each group of memory cells of a plurality of groups of memory cells of a plurality of memory cells selected for programming, enabling that group of memory cells for programming during a respective portion of the duration of the programming pulse of a corresponding voltage level of the plurality of different voltage levels, wherein memory cells of the plurality of memory cells selected for programming and having a particular intended data state are members of more than one of the groups of memory cells, and at least one of the groups of memory cells comprises a memory cell having the particular intended data state and a memory cell having a different intended data stateType: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Applicant: MICRON TECHNOLOGY, INC.Inventor: Aaron S. Yip
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Patent number: 11094379Abstract: Methods, as well as apparatus configured to perform similar methods, might include programming a plurality of memory cells to a particular data state of a plurality of data states, and, for each memory cell of the plurality of memory cells whose target data state is higher than the particular data state, determining a respective indication of a programming voltage level deemed sufficient to program that memory cell to a respective target threshold voltage corresponding to its respective target data state, and further programming that memory cell using a programming voltage level of a plurality of programming voltage levels corresponding to the respective indication of the programming voltage level deemed sufficient to program that memory cell to the respective target threshold voltage corresponding to its respective target data state.Type: GrantFiled: March 31, 2020Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 11094357Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.Type: GrantFiled: May 7, 2019Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Theodore T. Pekny
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Patent number: 11081165Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, with each driver circuitry connected to a respective block of memory cells.Type: GrantFiled: June 26, 2020Date of Patent: August 3, 2021Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip