Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit.