Patents by Inventor Aaron S. Yip
Aaron S. Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10014061Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.Type: GrantFiled: April 11, 2017Date of Patent: July 3, 2018Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Mark A. Helm
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Publication number: 20180137921Abstract: Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20180081753Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.Type: ApplicationFiled: September 16, 2016Publication date: March 22, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
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Patent number: 9875802Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: November 3, 2016Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20170330627Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to selected memory cells of a programming operation, assigning the selected memory cells to respective groups of memory cells each having a different range of threshold voltages, determining a respective value of VgVt for each group of memory cells, applying a subsequent programming pulse to the selected access line and having a particular voltage level determined in response to the value of VgVt for a particular group of memory cells, enabling the selected memory cells of the particular group of memory cells for programming while the subsequent programming pulse has the particular voltage level, and repeating for a next group of memory cells.Type: ApplicationFiled: August 1, 2017Publication date: November 16, 2017Applicant: MICRON TECHNOLOGY, INC.Inventor: Aaron S. Yip
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Publication number: 20170271014Abstract: Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of groups of memory cells to a particular range of threshold voltages, applying a stepped programming pulse to a selected access line connected to each memory cell of the plurality of groups of memory cells, and enabling each group of memory cells for programming when a voltage level of the stepped programming pulse corresponds to the respective indication of the programming voltage sufficient to program that group of memory cells to the particular range of threshold voltages.Type: ApplicationFiled: March 17, 2016Publication date: September 21, 2017Applicant: MICRON TECHNOLOGY, INC.Inventor: Aaron S. Yip
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Patent number: 9767909Abstract: Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of groups of memory cells to a particular range of threshold voltages, applying a stepped programming pulse to a selected access line connected to each memory cell of the plurality of groups of memory cells, and enabling each group of memory cells for programming when a voltage level of the stepped programming pulse corresponds to the respective indication of the programming voltage sufficient to program that group of memory cells to the particular range of threshold voltages.Type: GrantFiled: March 17, 2016Date of Patent: September 19, 2017Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Publication number: 20170076806Abstract: Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: November 3, 2016Publication date: March 16, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 9589978Abstract: In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs of the flight of stairs are respectively coupled to different tiers of memory cells, and a different pass transistor of the plurality of pass transistors is coupled to each of the stairs of the flight of stairs.Type: GrantFiled: February 25, 2016Date of Patent: March 7, 2017Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 9514829Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: December 3, 2015Date of Patent: December 6, 2016Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20160086672Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: December 3, 2015Publication date: March 24, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 9251860Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.Type: GrantFiled: June 10, 2015Date of Patent: February 2, 2016Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
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Patent number: 9218884Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: GrantFiled: January 13, 2014Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Publication number: 20150279432Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Applicant: MICRON TECHNOLOGY, INC.Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
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Patent number: 9070442Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.Type: GrantFiled: August 29, 2013Date of Patent: June 30, 2015Assignee: Micron Technology, Inc.Inventors: Aaron S. Yip, Mark A. Helm, Ramin Ghodsi
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Publication number: 20150063024Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Micron Technology, Inc.Inventors: Aaron S. YIP, Mark A. HELM, Ramin GHODSI
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Publication number: 20140126297Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: Micron Technology, Inc.Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron S. Yip
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Patent number: 5656949Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit.Type: GrantFiled: December 29, 1995Date of Patent: August 12, 1997Assignee: Cypress Semiconductor Corp.Inventors: Aaron S. Yip, Timothy M. Lacey, Anup K. Nayak, Rajiv Nema, Han-Kim Nguyen